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authorazidar2016-01-27 15:16:14 -0800
committerazidar2016-01-28 09:25:04 -0800
commit220c44eeb0778a9c789b15250f3ec5b634d5fc5d (patch)
treeba477d73833698e74e1e7dd56e4b7c7c562f11db /src
parent2428d391d02a9ff413884e073ae3e6ac37f2df2d (diff)
Fixed bug where needed to cast bit-operation inputs prior to verilog emission
Diffstat (limited to 'src')
-rw-r--r--src/main/stanza/passes.stanza12
1 files changed, 8 insertions, 4 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index f6fd1533..51e6581c 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -2523,6 +2523,10 @@ defn op-stream (doprim:DoPrim) -> Streamable :
match(type(doprim)) :
(t:UIntType) : e
(t:SIntType) : ["$signed(" e ")"]
+ defn cast-as (e:Expression) -> ? :
+ match(type(e)) :
+ (t:UIntType) : e
+ (t:SIntType) : ["$signed(" e ")"]
defn a0 () -> Expression : args(doprim)[0]
defn a1 () -> Expression : args(doprim)[1]
defn a2 () -> Expression : args(doprim)[2]
@@ -2565,10 +2569,10 @@ defn op-stream (doprim:DoPrim) -> Streamable :
match(type(a0())) :
(t:UIntType) : ["{1'b0," cast(a0()) "}"]
(t:SIntType) : [cast(a0())]
- NOT-OP : ["~ " cast(a0())]
- AND-OP : [cast(a0()) " & " cast(a1())]
- OR-OP : [cast(a0()) " | " cast(a1())]
- XOR-OP : [cast(a0()) " ^ " cast(a1())]
+ NOT-OP : ["~ " a0()]
+ AND-OP : [cast-as(a0()) " & " cast-as(a1())]
+ OR-OP : [cast-as(a0()) " | " cast-as(a1())]
+ XOR-OP : [cast-as(a0()) " ^ " cast-as(a1())]
AND-REDUCE-OP :
val v = Vector<Streamable>()
for b in 0 to to-int(long!(type(doprim))) do :