Added expand connect. Resolve now includes to working ir

7 files changed, 404 insertions, 66 deletions

diff --git a/src/main/scala/firrtl/Driver.scala b/src/main/scala/firrtl/Driver.scala
index 13e47e82..8876aac4 100644
--- a/src/main/scala/firrtl/Driver.scala
+++ b/src/main/scala/firrtl/Driver.scala
@@ -96,9 +96,11 @@ object Driver extends LazyLogging {
 // =====================================
     ScalaPass(resolve),
 // =====================================
-    StanzaPass("pull-muxes"),
+    StanzaPass("resolve"),
 // =====================================
-    StanzaPass("expand-connects"),
+    //StanzaPass("pull-muxes"),
+// =====================================
+    //StanzaPass("expand-connects"),
 // =====================================
     StanzaPass("remove-access"),
 // =====================================
diff --git a/src/main/scala/firrtl/IR.scala b/src/main/scala/firrtl/IR.scala
index a4da76a9..3656ef22 100644
--- a/src/main/scala/firrtl/IR.scala
+++ b/src/main/scala/firrtl/IR.scala
@@ -55,7 +55,7 @@ case object TAIL_OP extends PrimOp
 trait Expression extends AST
 case class Ref(name: String, tpe: Type) extends Expression
 case class SubField(exp: Expression, name: String, tpe: Type) extends Expression
-case class SubIndex(exp: Expression, value: BigInt, tpe: Type) extends Expression
+case class SubIndex(exp: Expression, value: Int, tpe: Type) extends Expression
 case class SubAccess(exp: Expression, index: Expression, tpe: Type) extends Expression
 case class Mux(cond: Expression, tval: Expression, fval: Expression, tpe: Type) extends Expression
 case class ValidIf(cond: Expression, value: Expression, tpe: Type) extends Expression
@@ -94,13 +94,13 @@ trait Type extends AST
 case class UIntType(width: Width) extends Type
 case class SIntType(width: Width) extends Type
 case class BundleType(fields: Seq[Field]) extends Type
-case class VectorType(tpe: Type, size: BigInt) extends Type
+case class VectorType(tpe: Type, size: Int) extends Type
 case class ClockType() extends Type
 case class UnknownType() extends Type
 
 trait Direction extends AST
-case object Input extends Direction
-case object Output extends Direction
+case object INPUT extends Direction
+case object OUTPUT extends Direction
 
 case class Port(info: Info, name: String, direction: Direction, tpe: Type) extends AST
 
diff --git a/src/main/scala/firrtl/Passes.scala b/src/main/scala/firrtl/Passes.scala
index 53429389..464cd057 100644
--- a/src/main/scala/firrtl/Passes.scala
+++ b/src/main/scala/firrtl/Passes.scala
@@ -3,6 +3,7 @@ package firrtl
 
 import com.typesafe.scalalogging.LazyLogging
 import scala.collection.mutable.HashMap
+import scala.collection.mutable.ArrayBuffer
 
 import Utils._
 import DebugUtils._
@@ -15,6 +16,7 @@ object Passes extends LazyLogging {
    //private def mapNameToPass = Map[String, Circuit => Circuit] (
    //  "infer-types" -> inferTypes
    //)
+   var mname = ""
    def nameToPass(name: String): Circuit => Circuit = {
      //mapNameToPass.getOrElse(name, throw new Exception("No Standard FIRRTL Pass of name " + name))
      name match {
@@ -28,8 +30,8 @@ object Passes extends LazyLogging {
    private def toField(p: Port): Field = {
      logger.debug(s"toField called on port ${p.serialize}")
      p.direction match {
-       case Input  => Field(p.name, REVERSE, p.tpe)
-       case Output => Field(p.name, DEFAULT, p.tpe)
+       case INPUT  => Field(p.name, REVERSE, p.tpe)
+       case OUTPUT => Field(p.name, DEFAULT, p.tpe)
      }
    }
    // ============== RESOLVE ALL ===================
@@ -38,23 +40,27 @@ object Passes extends LazyLogging {
          toWorkingIr _,
          resolveKinds _,
          inferTypes _,
-         resolveGenders _)
+         resolveGenders _,
+         pullMuxes _,
+         expandConnects _)
       val names = Seq(
          "To Working IR",
          "Resolve Kinds",
          "Infer Types",
-         "Resolve Genders")
+         "Resolve Genders",
+         "Pull Muxes",
+         "Expand Connects")
       var c_BANG = c
       (names, passes).zipped.foreach { 
          (n,p) => {
             println("Starting " + n)
             c_BANG = p(c_BANG)
+            println(c_BANG.serialize())
             println("Finished " + n)
          }
       }
       c_BANG
    }
-      
  
   // ============== TO WORKING IR ==================
   def toWorkingIr (c:Circuit) = {
@@ -74,19 +80,14 @@ object Passes extends LazyLogging {
         }
      }
      val modulesx = c.modules.map { m => 
+        mname = m.name
         m match {
            case m:InModule => InModule(m.info,m.name, m.ports, toStmt(m.body))
            case m:ExModule => m
         }
       }
-      println("Before To Working IR")
-      println(c.serialize())
-     val x = Circuit(c.info,modulesx,c.main)
-      println("After To Working IR")
-     println(x.serialize())
-     x
+     Circuit(c.info,modulesx,c.main)
    }
-   
   // ===============================================
 
   // ============== RESOLVE KINDS ==================
@@ -118,13 +119,13 @@ object Passes extends LazyLogging {
                sMap(find_stmt,s)
             }
             m.ports.foreach { p => kinds += (p.name -> PortKind()) }
-            println(kinds)
             m match {
                case m:InModule => find_stmt(m.body)
                case m:ExModule => false
             }
          }
        
+         mname = m.name
          find(m)   
          m match {
             case m:InModule => {
@@ -135,12 +136,7 @@ object Passes extends LazyLogging {
          }
       }
       val modulesx = c.modules.map(m => resolve_kinds(m,c))
-      println("Before Resolve Kinds")
-      println(c.serialize())
-      val x = Circuit(c.info,modulesx,c.main)
-      println("After Resolve Kinds")
-      println(x.serialize())
-      x
+      Circuit(c.info,modulesx,c.main)
    }
   // ===============================================
 
@@ -232,6 +228,7 @@ object Passes extends LazyLogging {
             }
          }
  
+         mname = m.name
          m.ports.foreach(p => types += (p.name -> p.tpe))
          m match {
             case m:InModule => InModule(m.info,m.name,m.ports,infer_types_s(m.body))
@@ -239,10 +236,9 @@ object Passes extends LazyLogging {
          }
        }
  
-   
-      // MAIN
       val modulesx = c.modules.map { 
          m => {
+            mname = m.name
             val portsx = m.ports.map(p => Port(p.info,p.name,p.direction,remove_unknowns(p.tpe)))
             m match {
                case m:InModule => InModule(m.info,m.name,portsx,m.body)
@@ -250,16 +246,11 @@ object Passes extends LazyLogging {
             }
          }
       }
-   
       modulesx.foreach(m => module_types += (m.name -> module_type(m)))
-      println("Before Infer Types")
-      println(c.serialize())
-      val x = Circuit(c.info,modulesx.map(m => infer_types(m)) , c.main )
-      println("After Infer Types")
-      println(x.serialize())
-      x
+      Circuit(c.info,modulesx.map({m => mname = m.name; infer_types(m)}) , c.main )
    }
 
+// =================== RESOLVE GENDERS =======================
    def resolveGenders (c:Circuit) = {
       def resolve_e (g:Gender)(e:Expression) : Expression = {
          e match {
@@ -306,6 +297,7 @@ object Passes extends LazyLogging {
       }
       val modulesx = c.modules.map { 
          m => {
+            mname = m.name
             m match {
                case m:InModule => {
                   val bodyx = resolve_s(m.body)
@@ -317,6 +309,244 @@ object Passes extends LazyLogging {
       }
       Circuit(c.info,modulesx,c.main)
    }
+  // ===============================================
+
+  // =============== PULL MUXES ====================
+   def pullMuxes (c:Circuit) : Circuit = {
+      def pull_muxes_e (e:Expression) : Expression = {
+         val ex = eMap(pull_muxes_e _,e) match {
+            case (e:WRef) => e
+            case (e:WSubField) => {
+               e.exp match {
+                  case (ex:Mux) => Mux(ex.cond,WSubField(ex.tval,e.name,e.tpe,e.gender),WSubField(ex.fval,e.name,e.tpe,e.gender),e.tpe)
+                  case (ex:ValidIf) => ValidIf(ex.cond,WSubField(ex.value,e.name,e.tpe,e.gender),e.tpe)
+                  case (ex) => e
+               }
+            }
+            case (e:WSubIndex) => {
+               e.exp match {
+                  case (ex:Mux) => Mux(ex.cond,WSubIndex(ex.tval,e.value,e.tpe,e.gender),WSubIndex(ex.fval,e.value,e.tpe,e.gender),e.tpe)
+                  case (ex:ValidIf) => ValidIf(ex.cond,WSubIndex(ex.value,e.value,e.tpe,e.gender),e.tpe)
+                  case (ex) => e
+               }
+            }
+            case (e:WSubAccess) => {
+               e.exp match {
+                  case (ex:Mux) => Mux(ex.cond,WSubAccess(ex.tval,e.index,e.tpe,e.gender),WSubAccess(ex.fval,e.index,e.tpe,e.gender),e.tpe)
+                  case (ex:ValidIf) => ValidIf(ex.cond,WSubAccess(ex.value,e.index,e.tpe,e.gender),e.tpe)
+                  case (ex) => e
+               }
+            }
+            case (e:Mux) => e
+            case (e:ValidIf) => e
+            case (e) => e
+         }
+         eMap(pull_muxes_e _,ex)
+      }
+
+      def pull_muxes (s:Stmt) : Stmt = eMap(pull_muxes_e _,sMap(pull_muxes _,s))
+
+      val modulesx = c.modules.map {
+         m => {
+            mname = m.name
+            m match {
+               case (m:InModule) => InModule(m.info,m.name,m.ports,pull_muxes(m.body))
+               case (m:ExModule) => m
+            }
+         }
+      }
+      Circuit(c.info,modulesx,c.main)
+   }
+  // ===============================================
+
+
+
+   // ============ EXPAND CONNECTS ==================
+   // ---------------- UTILS ------------------
+   def get_flip (t:Type, i:Int, f:Flip) : Flip = { 
+      if (i >= get_size(t)) error("Shouldn't be here")
+      val x = t match {
+         case (t:UIntType) => f
+         case (t:SIntType) => f
+         case (t:ClockType) => f
+         case (t:BundleType) => {
+            var n = i
+            var ret:Option[Flip] = None
+            t.fields.foreach { x => {
+               if (n < get_size(x.tpe)) {
+                  ret match {
+                     case None => ret = Some(get_flip(x.tpe,n,times(x.flip,f)))
+                     case ret => {}
+                  }
+               } else { n = n - get_size(x.tpe) }
+            }}
+            ret.asInstanceOf[Some[Flip]].get
+         }
+         case (t:VectorType) => {
+            var n = i
+            var ret:Option[Flip] = None
+            for (j <- 0 until t.size) {
+               if (n < get_size(t.tpe)) {
+                  ret = Some(get_flip(t.tpe,n,f))
+               } else {
+                  n = n - get_size(t.tpe)
+               }
+            }
+            ret.asInstanceOf[Some[Flip]].get
+         }
+      }
+      x
+   }
+   
+   def get_point (e:Expression) : Int = { 
+      e match {
+         case (e:WRef) => 0
+         case (e:WSubField) => {
+            var i = 0
+            tpe(e.exp).asInstanceOf[BundleType].fields.find { f => {
+               val b = f.name == e.name
+               if (!b) { i = i + get_size(f.tpe)}
+               b
+            }}
+            i
+         }
+         case (e:WSubIndex) => e.value * get_size(e.tpe)
+         case (e:WSubAccess) => get_point(e.exp)
+      }
+   }
+   
+   def create_exps (n:String, t:Type) : Seq[Expression] =
+      create_exps(WRef(n,t,ExpKind(),UNKNOWNGENDER))
+   def create_exps (e:Expression) : Seq[Expression] = {
+      e match {
+         case (e:Mux) => {
+            val e1s = create_exps(e.tval)
+            val e2s = create_exps(e.fval)
+            (e1s, e2s).zipped.map { 
+               (e1,e2) => Mux(e.cond,e1,e2,mux_type_and_widths(e1,e2))
+            }
+         }
+         case (e:ValidIf) => {
+            create_exps(e.value).map {
+               e1 => ValidIf(e.cond,e1,tpe(e1))
+            }
+         }
+         case (e) => {
+            tpe(e) match {
+               case (t:UIntType) => Seq(e)
+               case (t:SIntType) => Seq(e)
+               case (t:ClockType) => Seq(e)
+               case (t:BundleType) => {
+                  t.fields.flatMap {
+                     f => create_exps(WSubField(e,f.name,f.tpe,times(gender(e), f.flip)))
+                  }
+               }
+               case (t:VectorType) => {
+                  (0 until t.size).flatMap {
+                     i => create_exps(WSubIndex(e,i,t.tpe,gender(e)))
+                  }
+               }
+            }
+         }
+      }
+   }
+   
+   //---------------- Pass ---------------------
+   
+   def expandConnects (c:Circuit) : Circuit = { 
+      def expand_connects (m:InModule) : InModule = { 
+         mname = m.name
+         val genders = HashMap[String,Gender]()
+         def expand_s (s:Stmt) : Stmt = {
+            def set_gender (e:Expression) : Expression = {
+               eMap(set_gender _,e) match {
+                  case (e:WRef) => WRef(e.name,e.tpe,e.kind,genders(e.name))
+                  case (e:WSubField) => {
+                     val f = get_field(tpe(e.exp),e.name)
+                     val genderx = times(gender(e.exp),f.flip)
+                     WSubField(e.exp,e.name,e.tpe,genderx)
+                  }
+                  case (e:WSubIndex) => WSubIndex(e.exp,e.value,e.tpe,gender(e.exp))
+                  case (e:WSubAccess) => WSubAccess(e.exp,e.index,e.tpe,gender(e.exp))
+                  case (e) => e
+               }
+            }
+            s match {
+               case (s:DefWire) => { genders += (s.name -> BIGENDER); s }
+               case (s:DefRegister) => { genders += (s.name -> BIGENDER); s }
+               case (s:WDefInstance) => { genders += (s.name -> MALE); s }
+               case (s:DefMemory) => { genders += (s.name -> MALE); s }
+               case (s:DefPoison) => { genders += (s.name -> MALE); s }
+               case (s:DefNode) => { genders += (s.name -> MALE); s }
+               case (s:IsInvalid) => {
+                  val n = get_size(tpe(s.exp))
+                  val invalids = ArrayBuffer[Stmt]()
+                  val exps = create_exps(s.exp)
+                  for (i <- 0 until n) {
+                     val expx = exps(i)
+                     val gexpx = set_gender(expx)
+                     gender(gexpx) match {
+                        case BIGENDER => invalids += IsInvalid(s.info,expx)
+                        case FEMALE => invalids += IsInvalid(s.info,expx)
+                        case _ => {}
+                     }
+                  }
+                  if (invalids.length == 0) {
+                     Empty()
+                  } else if (invalids.length == 1) {
+                     invalids(0)
+                  } else Begin(invalids)
+               }
+               case (s:Connect) => {
+                  val n = get_size(tpe(s.loc))
+                  val connects = ArrayBuffer[Stmt]()
+                  val locs = create_exps(s.loc)
+                  val exps = create_exps(s.exp)
+                  for (i <- 0 until n) {
+                     val locx = locs(i)
+                     val expx = exps(i)
+                     val sx = get_flip(tpe(s.loc),i,DEFAULT) match {
+                        case DEFAULT => Connect(s.info,locx,expx)
+                        case REVERSE => Connect(s.info,expx,locx)
+                     }
+                     connects += sx
+                  }
+                  Begin(connects)
+               }
+               case (s:BulkConnect) => {
+                  val ls = get_valid_points(tpe(s.loc),tpe(s.exp),DEFAULT,DEFAULT)
+                  val connects = ArrayBuffer[Stmt]()
+                  val locs = create_exps(s.loc)
+                  val exps = create_exps(s.exp)
+                  ls.foreach { x => {
+                     val locx = locs(x._1)
+                     val expx = exps(x._2)
+                     val sx = get_flip(tpe(s.loc),x._1,DEFAULT) match {
+                        case DEFAULT => Connect(s.info,locx,expx)
+                        case REVERSE => Connect(s.info,expx,locx)
+                     }
+                     connects += sx
+                  }}
+                  Begin(connects)
+               }
+               case (s) => sMap(expand_s _,s)
+            }
+         }
+   
+         m.ports.foreach { p => genders += (p.name -> to_gender(p.direction)) }
+         InModule(m.info,m.name,m.ports,expand_s(m.body))
+      }
+   
+      val modulesx = c.modules.map { 
+         m => {
+            m match {
+               case (m:ExModule) => m
+               case (m:InModule) => expand_connects(m)
+            }
+         }
+      }
+      Circuit(c.info,modulesx,c.main)
+   }
 
   /** INFER TYPES
    *
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 3b849e45..0cab77f1 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -14,6 +14,7 @@ package firrtl
 import scala.collection.mutable.StringBuilder
 import java.io.PrintWriter
 import PrimOps._
+import scala.collection.mutable.ArrayBuffer
 //import scala.reflect.runtime.universe._
 
 object Utils {
@@ -26,6 +27,7 @@ object Utils {
    def ceil_log2(x: BigInt): BigInt = (x-1).bitLength
    val gen_names = Map[String,Int]()
    val delin = "_"
+   def BoolType () = { UIntType(IntWidth(1)) } 
    def firrtl_gensym (s:String):String = {
       firrtl_gensym(s,Map[String,Int]())
    }
@@ -143,7 +145,64 @@ object Utils {
      def serialize(implicit flags: FlagMap = FlagMap): String = op.getString
    }
 
-// =========== GENDER UTILS ============
+// =============== EXPANSION FUNCTIONS ================
+   def get_size (t:Type) : Int = {
+      t match {
+         case (t:BundleType) => {
+            var sum = 0
+            for (f <- t.fields) {
+               sum = sum + get_size(f.tpe)
+            }
+            sum
+         }
+         case (t:VectorType) => t.size * get_size(t.tpe)
+         case (t) => 1
+      }
+   }
+   def get_valid_points (t1:Type,t2:Type,flip1:Flip,flip2:Flip) : Seq[(Int,Int)] = {
+      //;println_all(["Inside with t1:" t1 ",t2:" t2 ",f1:" flip1 ",f2:" flip2])
+      (t1,t2) match {
+         case (t1:UIntType,t2:UIntType) => if (flip1 == flip2) Seq((0, 0)) else Seq()
+         case (t1:SIntType,t2:SIntType) => if (flip1 == flip2) Seq((0, 0)) else Seq()
+         case (t1:BundleType,t2:BundleType) => {
+            val points = ArrayBuffer[(Int,Int)]()
+            var ilen = 0
+            var jlen = 0
+            for (i <- 0 until t1.fields.size) {
+               for (j <- 0 until t2.fields.size) {
+                  val f1 = t1.fields(i)
+                  val f2 = t2.fields(j)
+                  if (f1.name == f2.name) {
+                     val ls = get_valid_points(f1.tpe,f2.tpe,times(flip1, f1.flip),times(flip2, f2.flip))
+                     for (x <- ls) {
+                        points += ((x._1 + ilen, x._2 + jlen))
+                     }
+                  }
+                  jlen = jlen + get_size(t2.fields(j).tpe)
+               }
+               ilen = ilen + get_size(t1.fields(i).tpe)
+               jlen = 0
+            }
+            points
+         }
+         case (t1:VectorType,t2:VectorType) => {
+            val points = ArrayBuffer[(Int,Int)]()
+            var ilen = 0
+            var jlen = 0
+            for (i <- 0 until scala.math.min(t1.size,t2.size)) {
+               val ls = get_valid_points(t1.tpe,t2.tpe,flip1,flip2)
+               for (x <- ls) {
+                  val y = ((x._1 + ilen), (x._2 + jlen))
+                  points += y
+               }
+               ilen = ilen + get_size(t1.tpe)
+               jlen = jlen + get_size(t2.tpe)
+            }
+            points
+         }
+      }
+   }
+// =========== GENDER/FLIP UTILS ============
    def swap (g:Gender) : Gender = {
       g match {
          case UNKNOWNGENDER => UNKNOWNGENDER
@@ -152,7 +211,24 @@ object Utils {
          case BIGENDER => BIGENDER
       }
    }
-// =========== FLIP UTILS ===============
+   def swap (d:Direction) : Direction = {
+      d match {
+         case OUTPUT => INPUT
+         case INPUT => OUTPUT
+      }
+   }
+   def swap (f:Flip) : Flip = {
+      f match {
+         case DEFAULT => REVERSE
+         case REVERSE => DEFAULT
+      }
+   }
+   def to_gender (d:Direction) : Gender = {
+      d match {
+         case INPUT => MALE
+         case OUTPUT => FEMALE
+      }
+   }
    def field_flip (v:Type,s:String) : Flip = {
       v match {
          case v:BundleType => {
@@ -165,6 +241,39 @@ object Utils {
          case v => DEFAULT
       }
    }
+   def get_field (v:Type,s:String) : Field = {
+      v match {
+         case v:BundleType => {
+            val ft = v.fields.find {p => p.name == s}
+            ft match {
+               case ft:Some[Field] => ft.get
+               case ft => error("Shouldn't be here"); Field("blah",DEFAULT,UnknownType())
+            }
+         }
+         case v => error("Shouldn't be here"); Field("blah",DEFAULT,UnknownType())
+      }
+   }
+   def times (flip:Flip,d:Direction) : Direction = times(flip, d)
+   def times (d:Direction,flip:Flip) : Direction = {
+      flip match {
+         case DEFAULT => d
+         case REVERSE => swap(d)
+      }
+   }
+   def times (g:Gender,flip:Flip) : Gender = times(flip, g)
+   def times (flip:Flip,g:Gender) : Gender = {
+      flip match {
+         case DEFAULT => g
+         case REVERSE => swap(g)
+      }
+   }
+   def times (f1:Flip,f2:Flip) : Flip = {
+      f2 match {
+         case DEFAULT => f1
+         case REVERSE => swap(f1)
+      }
+   }
+
 
 // =========== ACCESSORS =========
    def gender (e:Expression) : Gender = {
@@ -198,7 +307,7 @@ object Utils {
        case s:IsInvalid => UNKNOWNGENDER
      }
    def get_gender (p:Port) : Gender =
-     if (p.direction == Input) MALE else FEMALE
+     if (p.direction == INPUT) MALE else FEMALE
    def kind (e:Expression) : Kind =
       e match {
          case e:WRef => e.kind
@@ -240,10 +349,10 @@ object Utils {
           val write_type = BundleType(Seq(def_data,mask,addr,en,clk))
           val readwrite_type = BundleType(Seq(wmode,rdata,def_data,mask,addr,en,clk))
 
-          val mem_fields = Vector()
-          s.readers.foreach {x => mem_fields :+ Field(x,REVERSE,read_type)}
-          s.writers.foreach {x => mem_fields :+ Field(x,REVERSE,write_type)}
-          s.readwriters.foreach {x => mem_fields :+ Field(x,REVERSE,readwrite_type)}
+          val mem_fields = ArrayBuffer[Field]()
+          s.readers.foreach {x => mem_fields += Field(x,REVERSE,read_type)}
+          s.writers.foreach {x => mem_fields += Field(x,REVERSE,write_type)}
+          s.readwriters.foreach {x => mem_fields += Field(x,REVERSE,readwrite_type)}
           BundleType(mem_fields)
        }
        case s:DefInstance => UnknownType()
@@ -434,20 +543,23 @@ object Utils {
          case b: BulkConnect => s"${b.loc.serialize} <- ${b.exp.serialize}"
          case w: Conditionally => {
            var str = new StringBuilder(s"when ${w.pred.serialize} : ")
-           withIndent { str ++= w.conseq.serialize }
+           withIndent { str ++= newline + w.conseq.serialize }
            w.alt match {
               case s:Empty => str.result
               case s => {
                 str ++= newline + "else :"
-                withIndent { str ++= w.alt.serialize }
+                withIndent { str ++= newline + w.alt.serialize }
                 str.result
                 }
            }
          }
          case b: Begin => {
-           val s = new StringBuilder
-           b.stmts.foreach { s ++= newline ++ _.serialize }
-           s.result + debug(b)
+            val s = new StringBuilder
+            for (i <- 0 until b.stmts.size) {
+               if (i != 0) s ++= newline ++ b.stmts(i).serialize
+               else s ++= b.stmts(i).serialize
+            }
+            s.result + debug(b)
          } 
          case i: IsInvalid => s"${i.exp.serialize} is invalid"
          case s: Stop => s"stop(${s.clk.serialize}, ${s.en.serialize}, ${s.ret})"
@@ -497,8 +609,8 @@ object Utils {
          
      def toDirection(): Direction = {
        f match {
-         case DEFAULT => Output
-         case REVERSE => Input
+         case DEFAULT => OUTPUT
+         case REVERSE => INPUT
        }
      }
    }
@@ -544,15 +656,15 @@ object Utils {
    implicit class DirectionUtils(d: Direction) {
      def serialize(implicit flags: FlagMap = FlagMap): String = {
        val s = d match {
-         case Input => "input"
-         case Output => "output"
+         case INPUT => "input"
+         case OUTPUT => "output"
        } 
        s + debug(d)
      }
      def toFlip(): Flip = {
        d match {
-         case Input => REVERSE
-         case Output => DEFAULT
+         case INPUT => REVERSE
+         case OUTPUT => DEFAULT
        }
      }
    }
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index ccdb2e22..e9bc633c 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -53,8 +53,8 @@ class Visitor(val fullFilename: String) extends FIRRTLBaseVisitor[AST]
 
 	private def visitDir[AST](ctx: FIRRTLParser.DirContext): Direction =
     ctx.getText match {
-      case "input" => Input
-      case "output" => Output
+      case "input" => INPUT
+      case "output" => OUTPUT
     }
 
   // Match on a type instead of on strings?
@@ -66,7 +66,7 @@ class Visitor(val fullFilename: String) extends FIRRTLBaseVisitor[AST]
                      else SIntType( UnknownWidth() )
       case "Clock" => ClockType()
       case "{" => BundleType(ctx.field.map(visitField))
-      case _ => new VectorType( visitType(ctx.`type`), string2BigInt(ctx.IntLit.getText) )
+      case _ => new VectorType( visitType(ctx.`type`), string2Int(ctx.IntLit.getText) )
     }
   }
       
@@ -180,7 +180,7 @@ class Visitor(val fullFilename: String) extends FIRRTLBaseVisitor[AST]
           ctx.getChild(1).getText match {
             case "." => new SubField(visitExp(ctx.exp(0)), (ctx.id.getText), UnknownType())
             case "[" => if (ctx.exp(1) == null)  
-                          new SubIndex(visitExp(ctx.exp(0)), string2BigInt(ctx.IntLit(0).getText), UnknownType())
+                          new SubIndex(visitExp(ctx.exp(0)), string2Int(ctx.IntLit(0).getText), UnknownType())
                         else new SubAccess(visitExp(ctx.exp(0)), visitExp(ctx.exp(1)), UnknownType())
             // Assume primop
             case _ => DoPrim(visitPrimop(ctx.primop), ctx.exp.map(visitExp),
diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala
index 46c66c82..6fc57b8e 100644
--- a/src/main/scala/firrtl/WIR.scala
+++ b/src/main/scala/firrtl/WIR.scala
@@ -21,10 +21,9 @@ case object FEMALE extends Gender
 case object BIGENDER extends Gender
 case object UNKNOWNGENDER extends Gender
 
-case class BoolType() extends Type { UIntType(IntWidth(1)) } 
 case class WRef(name:String,tpe:Type,kind:Kind,gender:Gender) extends Expression
 case class WSubField(exp:Expression,name:String,tpe:Type,gender:Gender) extends Expression
-case class WSubIndex(exp:Expression,value:BigInt,tpe:Type,gender:Gender) extends Expression
+case class WSubIndex(exp:Expression,value:Int,tpe:Type,gender:Gender) extends Expression
 case class WSubAccess(exp:Expression,index:Expression,tpe:Type,gender:Gender) extends Expression
 case class WVoid() extends Expression
 case class WInvalid() extends Expression
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 6e8d89ad..a39c1287 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -29,6 +29,7 @@ public val standard-passes = to-list $ [
    VerilogWrap()
    SplitExp()
    VerilogRename()
+   Resolve()
 ]
 ;=============== WORKING IR ================================
 public definterface Kind
@@ -1680,7 +1681,8 @@ defn resolve (c:Circuit) -> Circuit :
    resolve-genders $
    check-types $
    infer-types $
-   resolve-kinds $ c
+   resolve-kinds $ 
+   to-working-ir $ c
 
 ;;================= Inline Instances ========================
 ;; Inlines instances. Assumes module with same name as the
@@ -2892,10 +2894,3 @@ defn lo-to-verilog (with-output:(() -> False) -> False, c:Circuit) :
    val c5 = verilog-rename(c4)
    ;println(c5)
    emit-verilog(with-output,c5)
-
-
-
-
-
-
-