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authorazidar2016-01-25 15:23:48 -0800
committerazidar2016-01-25 15:23:48 -0800
commitc94fd1bdd3f09339e2d4465398414c1b948b1aa3 (patch)
tree41d6d43cbbfec82f60e3a4c41d352d7595cab2bb /src
parent7e603c38b4cda6fd632c83893c2b0d29f8a898ed (diff)
Fixed width inference bug for muxes
Diffstat (limited to 'src')
-rw-r--r--src/main/stanza/passes.stanza2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 3f2417f2..f0ec188d 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -697,7 +697,7 @@ defn infer-types (c:Circuit) -> Circuit :
(e:WSubIndex) : WSubIndex(exp(e),value(e),sub-type(type(exp(e))),gender(e))
(e:WSubAccess) : WSubAccess(exp(e),index(e),sub-type(type(exp(e))),gender(e))
(e:DoPrim) : set-primop-type(e)
- (e:Mux) : Mux(cond(e),tval(e),fval(e),mux-type-and-widths(tval(e),tval(e)))
+ (e:Mux) : Mux(cond(e),tval(e),fval(e),mux-type-and-widths(tval(e),fval(e)))
(e:UIntValue|SIntValue) : e
defn infer-types-s (s:Stmt) -> Stmt :
match(s) :