Added verilog rename pass

2 files changed, 31 insertions, 0 deletions

diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index 1140e635..3ca4f8da 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -98,6 +98,7 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
       InferWidths()
       CheckWidths()
       ;===============
+      VerilogRename() 
       Verilog(with-output(c)) 
       ;===============
       ;ToRealIR()             
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index dbb489c4..3fba76de 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -2315,6 +2315,36 @@ defn lower-types (c:Circuit) -> Circuit :
    Circuit{info(c),_,main(c)} $
       for m in modules(c) map : lower-types(m)
 
+
+
+;============ RENAME VERILOG KEYWORDS =============
+
+public defstruct VerilogRename <: Pass
+public defmethod pass (b:VerilogRename) -> (Circuit -> Circuit) : verilog-rename
+public defmethod name (b:VerilogRename) -> String : "Verilog Rename"
+public defmethod short-name (b:VerilogRename) -> String : "Verilog Rename"
+
+defn verilog-rename (c:Circuit) -> Circuit :
+   defn verilog-rename-n (n:Symbol) -> Symbol :
+      if key?(v-keywords,n) : symbol-join([n `$])
+      else : n
+   defn verilog-rename-e (e:Expression) -> Expression :
+      match(e) :
+        (e:WRef) : WRef(verilog-rename-n(name(e)),type(e),kind(e),gender(e))
+        (e) : map(verilog-rename-e,e)
+   defn verilog-rename-s (s:Stmt) -> Stmt :
+      map{verilog-rename-n,_} $
+         map{verilog-rename-e,_} $
+            map(verilog-rename-s,s)
+      
+   Circuit{info(c),_,main(c)} $
+      for m in modules(c) map : 
+         val ports* = for p in ports(m) map :
+            Port(info(p),verilog-rename-n(name(p)),direction(p),type(p))
+         match(m) :
+            (m:InModule) : InModule(info(m),name(m),ports*,verilog-rename-s(body(m)))
+            (m:ExModule) : m
+
 ;============ VERILOG ==============
 
 public defstruct Verilog <: Pass :