| Age | Commit message (Expand) | Author |
|---|
| 2016-01-23 | Added prefix checker, now compliant with firrtl spec | azidar |
| 2016-01-23 | Changed chirrtl to not require known mask values | azidar |
| 2016-01-20 | WIP, need to update chirrtl with new mask syntax | azidar |
| 2016-01-17 | Forgot to add the changes | azidar |
| 2016-01-17 | Removed temporary files | azidar |
| 2016-01-17 | BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed tests | azidar |
| 2016-01-16 | Standard Verilog doesn't use Resolve(), but lists out the resolution passes i... | azidar |
| 2016-01-16 | Fixed bug in lowering memories that had aggregate data types | azidar |
| 2016-01-16 | Fixed bug in check-init that allows it to check on non-lowered things | azidar |
| 2016-01-16 | Moved back to create-exps instead of fast-create-exps to fix bug - fast-creat... | azidar |
| 2016-01-16 | Nodes must now be ground types | azidar |
| 2016-01-16 | Fixed up minor errors after rebase onto master | azidar |
| 2016-01-16 | Reworked Verilog emission of registers to if/else instead of ?: | azidar |
| 2016-01-16 | No longer split on muxes | azidar |
| 2016-01-16 | Commented back in Starting and Finishing for testing | azidar |
| 2016-01-16 | Sped up remove access by checking a condition | azidar |
| 2016-01-16 | Added more data in printout of time to compile | azidar |
| 2016-01-16 | printf no longer includes a new line | azidar |
| 2016-01-16 | Verilog emission no longer casts input to shr or bit select | azidar |
| 2016-01-16 | Added hashed on get flip | azidar |
| 2016-01-16 | Sped up some passes. Added global mname to allow easy per-module hashes for a... | azidar |
| 2016-01-16 | Made create-exps a bit faster | azidar |
| 2016-01-16 | Finished first cut at new firrtl - time for testing! Chirrtl requires masks t... | azidar |
| 2016-01-16 | Fixed a bunch of tests, and minor bugs | azidar |
| 2016-01-16 | Added src and test files | azidar |
| 2016-01-16 | WIP adding chirrtl | azidar |
| 2016-01-16 | WIP Almost there, need to generate enable connections | azidar |
| 2016-01-16 | WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl... | azidar |
| 2016-01-16 | WIP getting through tests | azidar |
| 2016-01-16 | Finished supporting nested accesses. Required some nuianced thinking. Pass al... | azidar |
| 2016-01-16 | WIP, hit semantic bug in WSubAccess | azidar |
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar |
| 2016-01-16 | WIP. Compiles and almost done with verilog backend. Need to think about emitt... | azidar |
| 2016-01-16 | WIP. Compiles and there's some output | azidar |
| 2016-01-16 | WIP. Compiles, need to test | azidar |
| 2016-01-16 | WIP | azidar |
| 2016-01-16 | WIP need to correctly output readwrite ports | azidar |
| 2016-01-16 | Merge branch 'scala' of github.com:ucb-bar/firrtl | azidar |
| 2016-01-16 | Added some comments | azidar |
| 2016-01-16 | Printf no longer adds a new line | azidar |
| 2016-01-16 | shift right does not cast input as signed | azidar |
| 2016-01-16 | Extraction inputs are no longer cast | azidar |
| 2016-01-16 | Width of multiply is sum of input widths | azidar |
| 2016-01-16 | Removed print statements | azidar |
| 2016-01-16 | Fixed inline-indexers bug where genders weren't properly calculated in | azidar |
| 2016-01-16 | Moved integer declaration inside module to be verilog (not system-verilog) co... | Adam Izraelevitz |
| 2016-01-16 | Stop now emits correct verilog to stop simulation, required passing a string ... | azidar |
| 2016-01-16 | Fixed bug in printf and stop to correctly print to STDERR | azidar |
| 2016-01-16 | Finished adding clocks to Stop and Print | azidar |
| 2015-12-11 | Add a renameall pass that renames nodes according to a user-provided | Paul Rigge |
