WIP need to correctly output readwrite ports

3 files changed, 102 insertions, 35 deletions

diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index 9bcf1fd9..8b25c10b 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -48,7 +48,7 @@ public defn get-sym-hash (m:InModule,keywords:Streamable<Symbol>) -> HashTable<S
    val sym-hash = HashTable<Symbol,Int>(symbol-hash)
    for k in keywords do :
       sym-hash[k] = 0
-   defn add-name (s:Symbol) -> False :
+   defn add-name (s:Symbol) -> Symbol :
       val s* = to-string(s)
       val i* = generated?(s*)
       match(i*) :
@@ -66,19 +66,11 @@ public defn get-sym-hash (m:InModule,keywords:Streamable<Symbol>) -> HashTable<S
                sym-hash[name] = max(num,digit)
             else :
                sym-hash[name] = digit
+      s
          
-   defn to-port (p:Port) -> False : add-name(name(p))
+   defn to-port (p:Port) : add-name(name(p))
    defn to-stmt (s:Stmt) -> Stmt :
-     match(s) :
-        (s:DefWire) : add-name(name(s))
-        (s:DefRegister) : add-name(name(s))
-        (s:DefInstance) : add-name(name(s))
-        (s:DefMemory) : add-name(name(s))
-        (s:DefNode) : add-name(name(s))
-        (s:DefPoison) : add-name(name(s))
-        (s:DefAccessor) : add-name(name(s))
-        (s) : false
-     map(to-stmt,s)
+     map{to-stmt,_} $ map(add-name,s)
 
    to-stmt(body(m))
    map(to-port,ports(m))
@@ -364,6 +356,18 @@ defmethod map (f: Expression -> Expression, e:Expression) -> Expression :
       (e:DoPrim) : DoPrim(op(e), map(f, args(e)), consts(e), type(e))
       (e) : e
 
+public defmulti map<?T> (f: Symbol -> Symbol, c:?T&Stmt) -> T
+defmethod map (f: Symbol -> Symbol, c:Stmt) -> Stmt :
+   match(c) :
+      (c:DefWire) : DefWire(info(c),f(name(c)),type(c))
+      (c:DefPoison) : DefPoison(info(c),f(name(c)),type(c))
+      (c:DefAccessor) : DefAccessor(info(c),f(name(c)), source(c), index(c),acc-dir(c))
+      (c:DefRegister) : DefRegister(info(c),f(name(c)), type(c), clock(c), reset(c))
+      (c:DefMemory) : DefMemory(info(c),f(name(c)), type(c), seq?(c), clock(c), size(c))
+      (c:DefNode) : DefNode(info(c),f(name(c)),value(c))
+      (c:DefInstance) : DefInstance(info(c),f(name(c)), module(c))
+      (c) : c
+
 public defmulti map<?T> (f: Expression -> Expression, c:?T&Stmt) -> T
 defmethod map (f: Expression -> Expression, c:Stmt) -> Stmt :
    match(c) :
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 02323181..35c1a92f 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -286,6 +286,11 @@ defmethod map (f: Expression -> Expression, c:DecFromIndexer) :
 defmethod map (f: Expression -> Expression, c:DecToIndexer) :
    DecToIndexer(info(c),f(index(c)), map(f, exps(c)), name(c), type(c))
 
+defmethod map (f: Symbol -> Symbol, c:DecFromIndexer) :
+   DecFromIndexer(info(c),index(c), exps(c), f(name(c)), type(c))
+defmethod map (f: Symbol -> Symbol, c:DecToIndexer) :
+   DecToIndexer(info(c),index(c), exps(c), f(name(c)), type(c))
+
 defmethod map (f: Type -> Type, e: WRef) :
    WRef(name(e), f(type(e)), kind(e), gender(e))
 defmethod map (f: Type -> Type, e: WSubfield) :
@@ -499,13 +504,14 @@ defn temp-elimination (c:Circuit) :
 ; Returns a new Circuit with Refs, Subfields, Indexes and DefAccessors 
 ;   replaced with IR-internal nodes that contain additional 
 ;   information (kind, gender)
+
 public defstruct ToWorkingIR <: Pass
 public defmethod pass (b:ToWorkingIR) -> (Circuit -> Circuit) : to-working-ir
 public defmethod name (b:ToWorkingIR) -> String : "Working IR"
 public defmethod short-name (b:ToWorkingIR) -> String : "to-working-ir"
 
 defn to-working-ir (c:Circuit) :
-   defn to-exp (e:Expression) :
+   defn to-exp (e:Expression) -> Expression :
       match(map(to-exp,e)) :
          (e:Ref) : WRef(name(e), type(e), NodeKind(), UNKNOWN-GENDER)
          (e:Subfield) : WSubfield(exp(e), name(e), type(e), UNKNOWN-GENDER)
@@ -879,32 +885,60 @@ defn expand-vector (e:Expression) -> List<Expression> :
    for i in 0 to size(t) map-append :
       list(WIndex(e,i,type(t),gender(e as ?))) ;always be WRef|WSubfield|WIndex
 
-defn expand-stmt (s:Stmt) -> Stmt :
-   match(s) :
-      (s:DefAccessor) : 
-         println-all-debug(["Matched DefAcc with " name(s)])
-         val mem? = match(source(s)) :
-            (e:WRef) : kind(e) typeof MemKind
-            (e) : false
-         if mem? : s
-         else :
-            val vtype = type(type(source(s)) as VectorType)
-            switch {acc-dir(s) == _} :
-               READ : DecToIndexer(info(s),index(s),expand-vector(source(s)),
-                                     name(s), vtype)
-               WRITE : DecFromIndexer(info(s),index(s),expand-vector(source(s)),
-                                    name(s), vtype)
-               INFER : error("Shouldn't be here")
-               RDWR : error("Haven't implemented RDWR yet")
-      (s) : map(expand-stmt,s)
+defn set-gender (e:Expression, g:Gender) -> Expression :
+   match(map(set-gender{_,g},e)) :
+      (e:WRef) : WRef(name(e),type(e),kind(e),g)
+      (e) : e
 
 defn expand-accessors (c:Circuit) :
+   var sh = HashTable<Symbol,Int>(symbol-hash)
+   var rds = HashTable<Symbol,Symbol>(symbol-hash)
+   var wrs = HashTable<Symbol,Symbol>(symbol-hash)
+
+   defn expand-exp (e:Expression) -> Expression :
+      match(map(expand-exp,e)) :
+         (e:WRef) : 
+            val n* = 
+               if key?(rds,name(e)) :
+                  switch {_ == gender(e)} :
+                     MALE : rds[name(e)]
+                     FEMALE : wrs[name(e)]
+                     BI-GENDER : error("Bigender")
+                     UNKNOWN-GENDER : error("Unknown")
+               else : name(e)
+            WRef(n*,type(e),kind(e),gender(e))
+         (e) : e
+                  
+   defn expand-stmt (s:Stmt) -> Stmt :
+      match(s) :
+         (s:DefAccessor) : 
+            println-all-debug(["Matched DefAcc with " name(s)])
+            if get-kind(source(s)) typeof MemKind: s
+            else :
+               val vtype = type(type(source(s)) as VectorType)
+               switch {acc-dir(s) == _} :
+                  READ : DecToIndexer(info(s),index(s),expand-vector(source(s)),name(s), vtype)
+                  WRITE : DecFromIndexer(info(s),index(s),expand-vector(source(s)),name(s), vtype)
+                  INFER : error("Shouldn't be here")
+                  RDWR :
+                    rds[name(s)] = firrtl-gensym(name(s),sh)
+                    val msrc = set-gender(source(s),MALE)
+                    val dti = DecToIndexer(info(s),index(s),expand-vector(msrc),rds[name(s)], vtype)
+                    wrs[name(s)] = firrtl-gensym(name(s),sh)
+                    val fsrc = set-gender(source(s),FEMALE)
+                    val dfi = DecFromIndexer(info(s),index(s),expand-vector(fsrc),wrs[name(s)], vtype)
+                    Begin(list(map(expand-exp,dti),map(expand-exp,dfi)))
+         (s) : map{expand-stmt,_} $ map(expand-exp,s)
+
    Circuit(info(c),modules*, main(c)) where :
       val modules* = 
          for m in modules(c) map :
             match(m) :
                (m:ExModule) : m
                (m:InModule) : 
+                  sh = get-sym-hash(m)
+                  rds = HashTable<Symbol,Symbol>(symbol-hash)
+                  wrs = HashTable<Symbol,Symbol>(symbol-hash)
                   InModule(info(m),name(m),ports(m),expand-stmt(body(m)))
 
 ;;=============== LOWERING TO GROUND TYPES =============================
@@ -1202,7 +1236,7 @@ defn lower-to-ground (c:Circuit) -> Circuit :
 ;               to-list $
 ;                  for (i in 1 to false, e in tail(exps(s))) stream : Conditionally(
 ;                     info(s),
-;                     equality(ref,UIntValue(BigIntLit(i),UnknownWidth())),
+;                    equality(ref,UIntValue(BigIntLit(i),UnknownWidth())),
 ;                     Connect(info(s),loc(s),e),
 ;                     EmptyStmt()
 ;                  )
@@ -1258,7 +1292,6 @@ defn inline-indexed-m (m:InModule) -> InModule :
          val index = index(indexed-dec as DecFromIndexer|DecToIndexer)
          val index-name =  firrtl-gensym(get-name(index),sh)
          val index-ref = WRef(index-name,type(index),NodeKind(),MALE) 
-      
          val replace-name = firrtl-gensym(get-name(indexer),sh)
          val replace-ref = WRef(replace-name,type(indexer),kind(indexer),gender(indexer)) 
       
@@ -1266,7 +1299,9 @@ defn inline-indexed-m (m:InModule) -> InModule :
          add(stmts, DefNode(info(indexed-dec),index-name,index))
          match(indexed-dec) :
             (s:DecFromIndexer) : 
-               if (gender(replace-ref) != FEMALE) : error("Shouldn't be here")
+               if (gender(replace-ref) != FEMALE) : 
+                  println(replace-ref)
+                  error("Shouldn't be here")
                for (i in 0 to false, e in exps(s)) do :
                   val eq = equality(index-ref,i)
                   val cond = Conditionally(info(s),eq,Connect(info(s),e,replace-ref),EmptyStmt())
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index b5196dac..7f949b11 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -277,9 +277,38 @@ defn emit-module (m:InModule) :
                   add(assigns,["assign " n* " = " emit(cons[n*]) ";"])
          (s:DefAccessor) : 
             val mem-declaration = decs[name(source(s) as Ref)] as DefMemory
+            defn jkjjjjjjj
             switch {_ == acc-dir(s)} :
                READ :
                   if seq?(mem-declaration) :
+                     val index* = Ref(firrtl-gensym(name(index(s) as Ref),sh),type(index(s)))
+                     add(regs,[ "reg  " get-width(type(index*)) " " name(index*) ";"]) ; register index for an additional cycle
+
+                     val w = width!(type(index*))
+                     add(inits,[name(index*) " = " rand-string(w)]) ; initialize registered index
+
+                     val my-clk-update = get?(updates,get-name(clock(mem-declaration)),Vector<Streamable>())
+                     add(my-clk-update,[name(index*) " <= " emit(index(s)) ";"]) ; register index
+                     updates[get-name(clock(mem-declaration))] = my-clk-update
+
+                     ; emit read accessor
+                     add(wires,["wire " get-width(type(source(s))) " " sym ";"])
+                     add(assigns,["assign " sym " = " emit(source(s)) "[" emit(index*) "];"])
+                  else :
+                     ; emit read accessor
+                     add(wires,["wire " get-width(type(source(s))) " " sym ";"])
+                     add(assigns,["assign " sym " = " emit(source(s)) "[" emit(index(s)) "];"])
+               WRITE : 
+                  val my-clk-update = get?(updates,get-name(clock(mem-declaration)),Vector<Streamable>())
+                  if key?(ens,sym) :
+                     add(my-clk-update,["if(" emit(ens[sym]) ") begin"])
+                     add(my-clk-update,["  " emit(source(s)) "[" emit(index(s)) "] <= " emit(cons[sym]) ";"])
+                     add(my-clk-update,["end"])
+                  else : 
+                     add(my-clk-update,[emit(source(s)) "[" emit(index(s)) "] <= " emit(cons[sym]) ";"])
+                  updates[get-name(clock(mem-declaration))] = my-clk-update
+               RDWR : 
+                  if seq?(mem-declaration) :
                      ; to make it sequential, register the index for an additional cycle
                      val index* = Ref(firrtl-gensym(name(index(s) as Ref),sh),type(index(s)))
                      add(regs,[ "reg  " get-width(type(index*)) " " name(index*) ";"]) 
@@ -296,7 +325,6 @@ defn emit-module (m:InModule) :
                      ; emit read accessor
                      add(wires,["wire " get-width(type(source(s))) " " sym ";"])
                      add(assigns,["assign " sym " = " emit(source(s)) "[" emit(index(s)) "];"])
-               WRITE : 
                   val my-clk-update = get?(updates,get-name(clock(mem-declaration)),Vector<Streamable>())
                   if key?(ens,sym) :
                      add(my-clk-update,["if(" emit(ens[sym]) ") begin"])