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authorazidar2016-01-16 14:12:57 -0800
committerazidar2016-01-16 14:28:19 -0800
commit480f26999b734271d5a730cc288644d5bef1b8d9 (patch)
tree7bcbdc0b05fdbed3be62bdc20089ca46393a0839 /src
parent17729b48b01db02ead9ab25a2c71e4ca8897c62e (diff)
Fixed bug in lowering memories that had aggregate data types
Diffstat (limited to 'src')
-rw-r--r--src/main/stanza/passes.stanza3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index e34a8682..45aaf755 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -2185,7 +2185,7 @@ defn lower-types (m:Module) -> Module :
defn lower-types-e (e:Expression) -> Expression :
match(e) :
(e:WRef|UIntValue|SIntValue) : e
- (e:WSubField) :
+ (e:WSubField|WSubIndex) :
match(kind(e)) :
(k:InstanceKind) :
val names = expand-name(e)
@@ -2198,7 +2198,6 @@ defn lower-types (m:Module) -> Module :
lower-mem(e)[0]
else : e
(k) : WRef(lowered-name(e),type(e),kind(e),gender(e))
- (e:WSubIndex) : WRef(lowered-name(e),type(e),kind(e),gender(e))
(e:DoPrim) : map(lower-types-e,e)
match(map(lower-types-e,s)) :
(s:DefWire|DefPoison) :