WIP. Compiles and there's some output

3 files changed, 40 insertions, 20 deletions

diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index bed150ba..9dda33fe 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -71,11 +71,12 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
       ;Pad()                    ;R
       ConstProp()              ;R
       SplitExp()               ;R
+      LowerTypes()               ;R
       ;CheckWidths()            ;R
       ;CheckHighForm()          ;R
       ;CheckLowForm()           ;R
       ;CheckInitialization()    ;R
-      ;Verilog(with-output(c))  ;R
+      Verilog(with-output(c))  ;R
    ]
 
 public defstruct StandardFIRRTL <: Compiler :
diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza
index b3da3c0b..c1876dbb 100644
--- a/src/main/stanza/firrtl-test-main.stanza
+++ b/src/main/stanza/firrtl-test-main.stanza
@@ -34,24 +34,24 @@ defpackage firrtl-main :
    ;import firrtl/custom-passes
    ;import firrtl/custom-compiler
 
-;defn set-printvars! (p:List<Char>) :
-;   if contains(p,'t') : PRINT-TYPES = true
-;   if contains(p,'k') : PRINT-KINDS = true
-;   if contains(p,'w') : PRINT-WIDTHS = true
-;   if contains(p,'T') : PRINT-TWIDTHS = true
-;   if contains(p,'g') : PRINT-GENDERS = true
-;   if contains(p,'c') : PRINT-CIRCUITS = true
-;   if contains(p,'d') : PRINT-DEBUG = true
-;   if contains(p,'i') : PRINT-INFO = true
-;
-;defn get-passes (pass-names:List<String>) -> List<Pass> :
-;   for n in pass-names map :
-;      val p = for p in standard-passes find :
-;         n == short-name(p)
-;      if p == false :
-;         error(to-string $ ["Unrecognized pass flag: " n])
-;      p as Pass
-;         
+defn set-printvars! (p:List<Char>) :
+   if contains(p,'t') : PRINT-TYPES = true
+   if contains(p,'k') : PRINT-KINDS = true
+   if contains(p,'w') : PRINT-WIDTHS = true
+   if contains(p,'T') : PRINT-TWIDTHS = true
+   if contains(p,'g') : PRINT-GENDERS = true
+   if contains(p,'c') : PRINT-CIRCUITS = true
+   if contains(p,'d') : PRINT-DEBUG = true
+   if contains(p,'i') : PRINT-INFO = true
+
+defn get-passes (pass-names:List<String>) -> List<Pass> :
+   for n in pass-names map :
+      val p = for p in standard-passes find :
+         n == short-name(p)
+      if p == false :
+         error(to-string $ ["Unrecognized pass flag: " n])
+      p as Pass
+         
 defn main () :
    val args = commandline-arguments()
    var input = false
@@ -76,7 +76,10 @@ defn main () :
       else if s == "-p" : last-s = s
       else if s == "-s" : last-s = s
       else if s == "-m" : last-s = s
+<<<<<<< HEAD
       else if s == "-b" : last-s = s
+=======
+>>>>>>> WIP. Compiles and there's some output
       else :
          if last-s == "-i" : input = args[i]
          if last-s == "-o" : output = args[i]
@@ -85,7 +88,10 @@ defn main () :
          if last-s == "-p" : printvars = to-string([printvars args[i]])
          if last-s == "-s" : add(pass-args,args[i])
          if last-s == "-m" : add(firms,args[i])
+<<<<<<< HEAD
          if last-s == "-b" : backend = args[i]
+=======
+>>>>>>> WIP. Compiles and there's some output
 
    var with-output = 
       fn (f:()->False) : 
@@ -106,8 +112,13 @@ defn main () :
             CURRENT-OUTPUT-STREAM = prev-stream
             close(out-stream)
 
+<<<<<<< HEAD
    if compiler == false and backend == false and length(pass-names) == 0 :
       error("Must specify a compiler or a backend. Use -X flag or -b flag.")
+=======
+   if compiler == false and length(pass-names) == 0 :
+      error("Must specify a compiler. Use -X flag.")
+>>>>>>> WIP. Compiles and there's some output
 
    val lexed = lex-file(input as String)
    val circuit = parse-firrtl(lexed)
@@ -130,19 +141,27 @@ defn main () :
    set-printvars!(to-list(printvars))
    
    if compiler == false :
+<<<<<<< HEAD
       var c*:Circuit = run-passes(circuit*,get-passes(to-list(pass-names)))
       switch {_ == backend} :
         "verilog" : run-backend(c*,StandardVerilog(with-output))
         "firrtl" : run-backend(c*,StandardFIRRTL(with-output))
         else : error("Invalid backend flag!")
+=======
+      run-passes(circuit*,get-passes(to-list(pass-names)))
+>>>>>>> WIP. Compiles and there's some output
    else :
       switch {_ == compiler} :
          ;"flo" : error("Flo backend not currently supported.")
             ; run-passes(circuit*,StandardFlo(with-output))
          "verilog" : run-passes(circuit*,StandardVerilog(with-output))
+<<<<<<< HEAD
          "firrtl" : run-passes(circuit*,StandardFIRRTL(with-output))
          "lofirrtl" : run-passes(circuit*,StandardLoFIRRTL(with-output))
          "verilute" : run-passes(circuit*,InstrumentedVerilog(with-output,to-list $ pass-args))
+=======
+         ;"verilute" : run-passes(circuit*,InstrumentedVerilog(with-output,to-list $ pass-args))
+>>>>>>> WIP. Compiles and there's some output
          else : error("Invalid compiler flag")
 
    CURRENT-OUTPUT-STREAM = prev-out
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 897bb94d..4dbd55d8 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -366,7 +366,7 @@ defn remove-unknowns-w (w:Width) -> Width :
    match(w) :
       (w:UnknownWidth) : VarWidth(firrtl-gensym(`w,width-name-hash))
       (w) : w
-defn remove-unknowns (t:Type) -> Type : t;mapr(remove-unknowns-w,t) TODO FIX!!!
+defn remove-unknowns (t:Type) -> Type : mapr(remove-unknowns-w,t)
 
 defmethod equal? (w1:Width,w2:Width) -> True|False :
    match(w1,w2) :