Finished adding clocks to Stop and Print

5 files changed, 43 insertions, 31 deletions

diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index 5bc1ea68..d3f60646 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -158,10 +158,12 @@ public defstruct Connect <: Stmt : ;LOW
 public defstruct StopStmt <: Stmt : ;LOW
    info: FileInfo with: (as-method => true)
    ret: Int
+   clk: Expression
 public defstruct PrintfStmt <: Stmt : ;LOW
    info: FileInfo with: (as-method => true)
    string: String
    args: List<Expression>
+   clk: Expression
 
 public defstruct EmptyStmt <: Stmt ;LOW
 
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index a4ca89f7..c4480afb 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -246,8 +246,8 @@ defsyntax firrtl :
       stmt = (write accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name,s,i,WRITE)
       stmt = (infer accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name,s,i,INFER)
       stmt = (rdwr accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name,s, i,RDWR)
-      stmt = (stop(?ret:#int)) : StopStmt(first-info(form),ret)
-      stmt = (printf(?str:#string ?es:#exp ...)) : PrintfStmt(first-info(form),str,es)
+      stmt = (stop( ?clk:#exp!, ?ret:#int)) : StopStmt(first-info(form),ret,clk)
+      stmt = (printf( ?clk:#exp!, ?str:#string ?es:#exp ...)) : PrintfStmt(first-info(form),str,es,clk)
       stmt = (?s:#stmt/when) : s
 
       stmt = (?x:#exp := ?y:#exp!) : Connect(first-info(form),x, y)
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index dbcf3b73..9bcf1fd9 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -279,9 +279,9 @@ defmethod print (o:OutputStream, c:Stmt) :
       (c:EmptyStmt) :
          print(o, "skip")
       (c:StopStmt) :
-         print-all(o, ["stop(" ret(c) ")"])
+         print-all(o, ["stop(" clk(c) ", " ret(c) ")"])
       (c:PrintfStmt) :
-         print-all(o, ["printf("]) ;"
+         print-all(o, ["printf(" clk(c) ", " ]) ;"
          print-all(o, join(List(escape(string(c)),args(c)), ", "))
          print(o, ")")
          
@@ -376,7 +376,8 @@ defmethod map (f: Expression -> Expression, c:Stmt) -> Stmt :
       (c:Connect) : Connect(info(c),f(loc(c)), f(exp(c)))
       (c:BulkConnect) : BulkConnect(info(c),f(loc(c)), f(exp(c)))
       (c:OnReset) : OnReset(info(c),f(loc(c)),f(exp(c)))
-      (c:PrintfStmt) : PrintfStmt(info(c),string(c),map(f,args(c)))
+      (c:PrintfStmt) : PrintfStmt(info(c),string(c),map(f,args(c)),f(clk(c)))
+      (c:StopStmt) : StopStmt(info(c),ret(c),f(clk(c)))
       (c) : c
 
 public defmulti map<?T> (f: Stmt -> Stmt, c:?T&Stmt) -> T
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index e31b30a9..7b5618aa 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -365,7 +365,7 @@ defn remove-special-chars (c:Circuit) :
          (s:Connect) : Connect(info(s),rename-e(loc(s)),rename-e(exp(s)))
          (s:EmptyStmt) : s
          (s:StopStmt) : s
-         (s:PrintfStmt) : PrintfStmt(info(s),string(s),map(rename-e,args(s)))
+         (s:PrintfStmt) : PrintfStmt(info(s),string(s),map(rename-e,args(s)),rename-e(clk(s)))
 
    Circuit(info(c),modules*, rename(main(c))) where :
       val modules* =
@@ -821,7 +821,7 @@ defn resolve-genders (c:Circuit) :
                val alt* = resolve-stmt(alt(s))
                Conditionally(info(s),pred*,conseq*,alt*)
             (s:PrintfStmt) : 
-               PrintfStmt(info(s),string(s),map(resolve-expr{_,MALE},args(s)))
+               PrintfStmt(info(s),string(s),map(resolve-expr{_,MALE},args(s)),clk(s))
             (s) : map(resolve-stmt,s)
 
       defn resolve-expr (e:Expression,desired:Gender) -> Expression :
@@ -1134,7 +1134,7 @@ defn lower (body:Stmt) -> Stmt :
             Conditionally(info(s),exp(head $ expand-expr(pred(s))),lower-stmt(conseq(s)),lower-stmt(alt(s)))
          (s:PrintfStmt) :
             val args* = for x in args(s) map : exp(head(expand-expr(x)))
-            PrintfStmt(info(s),string(s),args*)
+            PrintfStmt(info(s),string(s),args*,clk(s))
          (s:Begin|EmptyStmt|StopStmt) : map(lower-stmt,s)
 
    lower-stmt(body)
@@ -2089,7 +2089,7 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod
             add(v,WGeq(width!(type(l)),width!(type(e))))
             Connect(info(s),l,e)
          (s:PrintfStmt) : 
-            PrintfStmt(info(s),string(s),map(gen-constraints,args(s)))
+            PrintfStmt(info(s),string(s),map(gen-constraints,args(s)),gen-constraints(clk(s)))
          (s:Conditionally) : 
             val p = gen-constraints(pred(s))
             add(v,WGeq(width!(type(p)),LongWidth(1)))
@@ -2373,7 +2373,7 @@ defn split-exp (c:Circuit) :
                (c:PrintfStmt) :
                   val args* = for x in args(c) map :
                      map(split-exp-e{_,false,info(c)},x)
-                  val conseq* = PrintfStmt(info(c),string(c),args*)
+                  val conseq* = PrintfStmt(info(c),string(c),args*,clk(c))
                   add(v,Conditionally(info(s),pred*,conseq*,alt(s)))
                (c:StopStmt) :
                   add(v,Conditionally(info(s),pred*,c,alt(s)))
@@ -2383,7 +2383,7 @@ defn split-exp (c:Circuit) :
          (s:PrintfStmt) : 
             val args* = for x in args(s) map :
                map(split-exp-e{_,false,info(s)},x)
-            add(v,PrintfStmt(info(s),string(s),args*))
+            add(v,PrintfStmt(info(s),string(s),args*,clk(s)))
          (s:DefNode) : 
             val exp* = map(split-exp-e{_,name(s),info(s)},value(s))
             add(v,DefNode(info(s),name(s),exp*))
@@ -2543,7 +2543,7 @@ defn pad-widths-s (s:Stmt) -> Stmt :
          val args* = for x in args(s) map :
             val i = int-width!(type(x))
             pad-widths-e(i,x)
-         PrintfStmt(info(s),string(s),args*)
+         PrintfStmt(info(s),string(s),args*,clk(s))
       (s:DefNode) : 
          val i = int-width!(type(value(s)))
          val exp* = pad-widths-e(i,value(s))
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index 5cf42323..de11229d 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -182,7 +182,7 @@ defn emit-module (m:InModule) :
    val decs = HashTable<Symbol,Stmt>(symbol-hash) ; all declarations, for fast lookups
    val cons = HashTable<Symbol,Expression>(symbol-hash) ; all connections
    val ens = HashTable<Symbol,Expression>(symbol-hash) ; all enables
-   val simuls = Vector<Streamable>()
+   val simuls = HashTable<Symbol,Vector<Streamable>>(symbol-hash)
    defn build-table (s:Stmt) -> False :
       match(s) :
          (s:DefWire|DefPoison|DefRegister|DefAccessor|DefMemory|DefNode|DefInstance) : 
@@ -195,19 +195,27 @@ defn emit-module (m:InModule) :
                   ens[n] = pred(s)
                   cons[n] = exp(conseq(s) as Connect)
                (c:PrintfStmt) :
-                  add(simuls,["if(" emit(pred(s)) ") begin"])
-                  add(simuls,["  $fdisplay(32/'h80000002," string-join(List(escape(string(c)),map(emit,args(c))), ", ") ");"])
-                  add(simuls,["end"])
+                  val my-clk-simuls = get?(simuls,get-name(clk(c)),Vector<Streamable>())
+                  add(my-clk-simuls,["if(" emit(pred(s)) ") begin"])
+                  add(my-clk-simuls,["  $fdisplay(32/'h80000002," string-join(List(escape(string(c)),map(emit,args(c))), ", ") ");"])
+                  add(my-clk-simuls,["end"])
+                  simuls[get-name(clk(c))] = my-clk-simuls
                (c:StopStmt) : 
-                  add(simuls,["if(" emit(pred(s)) ") begin"])
-                  add(simuls,["  $fdisplay(32/'h80000002," ret(c) ");"])
-                  add(simuls,["  $finish;"])
-                  add(simuls,["end"])
+                  val my-clk-simuls = get?(simuls,get-name(clk(c)),Vector<Streamable>())
+                  add(my-clk-simuls,["if(" emit(pred(s)) ") begin"])
+                  add(my-clk-simuls,["  $fdisplay(32/'h80000002," ret(c) ");"])
+                  add(my-clk-simuls,["  $finish;"])
+                  add(my-clk-simuls,["end"])
+                  simuls[get-name(clk(c))] = my-clk-simuls
          (s:PrintfStmt) : 
-            add(simuls,["$fdisplay(32/'h80000002," string-join(List(escape(string(s)),map(emit,args(s))), ", ") ");"])
+            val my-clk-simuls = get?(simuls,get-name(clk(s)),Vector<Streamable>())
+            add(my-clk-simuls,["$fdisplay(32/'h80000002," string-join(List(escape(string(s)),map(emit,args(s))), ", ") ");"])
+            simuls[get-name(clk(s))] = my-clk-simuls
          (c:StopStmt) : 
-            add(simuls,["$fdisplay(32/'h80000002," ret(c) ");"])
-            add(simuls,["$finish;"])
+            val my-clk-simuls = get?(simuls,get-name(clk(c)),Vector<Streamable>())
+            add(my-clk-simuls,["$fdisplay(32/'h80000002," ret(c) ");"])
+            add(my-clk-simuls,["$finish;"])
+            simuls[get-name(clk(c))] = my-clk-simuls
          (s:Connect) : 
             val n = get-name(loc(s))
             cons[n] = exp(s)
@@ -353,14 +361,15 @@ defn emit-module (m:InModule) :
             println-all(u)
          println("  end")
 
-   if length(simuls) != 0 :
-      println("`ifndef SYNTHESIS")
-      println("  always @(*) begin")
-      for x in simuls do :
-         print("    ")
-         println-all(x)
-      println("  end")
-      println("`endif")
+   for x in simuls do :
+      if length(value(x)) != 0 :
+         println("`ifndef SYNTHESIS")
+         println-all(["  always @(posedge " key(x) ") begin"])
+         for u in value(x) do :
+            print("    ")
+            println-all(u)
+         println("  end")
+         println("`endif")
       
    println("endmodule")