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authorazidar2015-12-11 10:44:27 -0800
committerazidar2015-12-11 10:44:27 -0800
commit2beab33ac298470bc04caf1c3b7a5a0d17d465d4 (patch)
tree137717e2bf63ebc838ab63c412f133983dd59898 /src
parent2b04de4567e0ade01fdbfa6921fae91537180461 (diff)
Added LoFirrtl compiler, can be called with -X lofirrtl
Diffstat (limited to 'src')
-rw-r--r--src/main/stanza/compilers.stanza37
-rw-r--r--src/main/stanza/firrtl-test-main.stanza1
2 files changed, 38 insertions, 0 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index edbf5c66..4d12ddcb 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -88,6 +88,43 @@ public defmethod passes (c:StandardFIRRTL) -> List<Pass> :
]
+public defstruct StandardLoFIRRTL <: Compiler :
+ with-output : (() -> False) -> False with: (as-method => true)
+public defmethod backend (c:StandardLoFIRRTL) -> List<Pass> :
+ to-list $ [ FIRRTL(with-output(c)) ]
+public defmethod passes (c:StandardLoFIRRTL) -> List<Pass> :
+ to-list $ [
+ RemoveSpecialChars() ;R
+ ;RemoveScopes() ;R
+ CheckHighForm() ;R
+ TempElimination() ;R
+ ToWorkingIR() ;R -> W
+ ResolveKinds() ;W
+ InferTypes() ;R
+ ResolveGenders() ;W
+ CheckGenders() ;W
+ CheckKinds() ;W
+ CheckTypes() ;R
+ ExpandAccessors() ;W
+ LowerToGround() ;W
+ ;ExpandIndexedConnects() ;W
+ InlineIndexed()
+ InferTypes() ;R
+ CheckGenders() ;W
+ ExpandWhens() ;W
+ InferWidths() ;R
+ ToRealIR() ;W -> R
+ CheckWidths() ;R
+ Pad() ;R
+ ConstProp() ;R
+ SplitExp() ;R
+ CheckWidths() ;R
+ CheckHighForm() ;R
+ CheckLowForm() ;R
+ CheckInitialization() ;R
+ FIRRTL(with-output(c)) ;R
+ ]
+
;============= DRIVER ======================================
public defn run-backend (c:Circuit,comp:Compiler) :
run-passes(c,backend(comp))
diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza
index 2f8e84d5..238a2afc 100644
--- a/src/main/stanza/firrtl-test-main.stanza
+++ b/src/main/stanza/firrtl-test-main.stanza
@@ -141,6 +141,7 @@ defn main () :
; run-passes(circuit*,StandardFlo(with-output))
"verilog" : run-passes(circuit*,StandardVerilog(with-output))
"firrtl" : run-passes(circuit*,StandardFIRRTL(with-output))
+ "lofirrtl" : run-passes(circuit*,StandardLoFIRRTL(with-output))
"verilute" : run-passes(circuit*,InstrumentedVerilog(with-output,to-list $ pass-args))
else : error("Invalid compiler flag")