diff options
| author | azidar | 2016-01-14 13:27:09 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 11:45:00 -0800 |
| commit | e2b0b6548cdaad19034ee32571faac4a87943849 (patch) | |
| tree | ea45ffe0c1dcf41575f2fd507b70558aa23ea8d9 /src | |
| parent | 24789a974ce55a9b83133bdd5dd7a64241e447d6 (diff) | |
Fixed inline-indexers bug where genders weren't properly calculated in
Lower Types pass. #53
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 2 | ||||
| -rw-r--r-- | src/main/stanza/passes.stanza | 23 |
2 files changed, 20 insertions, 5 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index 4d12ddcb..88a4141a 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -62,6 +62,8 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : ;ExpandIndexedConnects() ;W InlineIndexed() InferTypes() ;R + ResolveGenders() ;W + CheckTypes() ;R CheckGenders() ;W ExpandWhens() ;W InferWidths() ;R diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 7b5618aa..6200e956 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -977,10 +977,10 @@ defn expand-expr (e:Expression) -> List<EF> : if inst?(e) : for f in fields(type(e) as BundleType) map-append : for x in generate-entry(name(f),type(f)) map : - EF(WSubfield(e,name(x),type(x),gender(e)),flip(f) * flip(x)) + EF(WSubfield(e,name(x),type(x),gender(e) * flip(x)),flip(f) * flip(x)) else : for x in generate-entry(name(e),type(e)) map : - EF(WRef(name(x),type(x),kind(e),gender(e)), flip(x)) + EF(WRef(name(x),type(x),kind(e),gender(e) * flip(x)), flip(x)) (e:WSubfield) : val f = {_ as Field} $ for f in fields(type(exp(e)) as BundleType) find : name(f) == name(e) @@ -1002,8 +1002,16 @@ defn expand-expr (e:Expression) -> List<EF> : ;val v = exp(head(expand-expr(value(e)))) ;list(EF(Pad(v,width(e),type(e)),DEFAULT)) (e:DoPrim) : - val args = for x in args(e) map : exp(head(expand-expr(x))) - list(EF(DoPrim(op(e),args,consts(e),type(e)),DEFAULT)) + println(e) + val vargs = Vector<Expression>() + val vflips = Vector<Flip>() + for x in args(e) do : + val r = head(expand-expr(x)) + add(vargs,exp(r)) + add(vflips,flip(r)) + println(vargs) + println(vflips) + list(EF(DoPrim(op(e),to-list(vargs),consts(e),type(e)),DEFAULT)) (e) : list(EF(e,DEFAULT)) defn lower-ports (ports:List<Port>) -> List<Port> : @@ -1267,7 +1275,12 @@ defn inline-indexed-m (m:InModule) -> InModule : val cond = Conditionally(info(s),eq,Connect(info(s),e,replace-ref),EmptyStmt()) add(stmts,map(inline-indexed-s,cond)) (s:DecToIndexer) : - if (gender(replace-ref) != MALE) : error("Shouldn't be here") + if (gender(replace-ref) != MALE) : + println(gender(replace-ref)) + println(replace-ref) + println(indexed-dec) + println(indexer) + error("Shouldn't be here") val cnct = Connect(info(s),replace-ref,head(exps(s))) add(stmts,map(inline-indexed-e,cnct)) ;println-all(["exps: " exps(s)]) |
