Moved integer declaration inside module to be verilog (not system-verilog) compliant

1 files changed, 2 insertions, 1 deletions

diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index 15c6ac6a..0e1c97c3 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -307,7 +307,6 @@ defn emit-module (m:InModule) :
                   updates[get-name(clock(mem-declaration))] = my-clk-update
             
    ;==== Actually printing module =====
-   if length(simuls) != 0 : print-all(["integer STDERR = 32'h80000002;\n"])
    val port-indent = "    "
    print-all(["module " name(m) "(\n"])
    for (p in ports(m),i in 1 to false) do :
@@ -322,6 +321,8 @@ defn emit-module (m:InModule) :
             add(assigns,["assign " name(p) " = " emit(cons[name(p)]) ";"])
    if length(ports(m)) == 0 : print(");\n")
 
+   if length(simuls) != 0 : print-all(["  integer STDERR = 32'h80000002;\n"])
+
    for w in wires do :
       print("  ")
       println-all(w)