diff options
| author | azidar | 2015-12-11 12:40:32 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 11:45:00 -0800 |
| commit | 1d63b78f41ab3c3de88a5bb167f7412186dd677a (patch) | |
| tree | af5c66ca8aac0e870b17a634e1f4a96c9f9fc832 /src | |
| parent | e562ef9773d5c9e368878a01c53b168fde36e9a0 (diff) | |
Stop now emits correct verilog to stop simulation, required passing a string not and integer
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/stanza/verilog.stanza | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index 7196fe82..15c6ac6a 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -203,7 +203,7 @@ defn emit-module (m:InModule) : (c:StopStmt) : val my-clk-simuls = get?(simuls,get-name(clk(c)),Vector<Streamable>()) add(my-clk-simuls,["if(" emit(pred(s)) ") begin"]) - add(my-clk-simuls,[" $fdisplay(STDERR," ret(c) ");"]) + add(my-clk-simuls,[" $fdisplay(STDERR,\"" ret(c) "\");"]) add(my-clk-simuls,[" $finish;"]) add(my-clk-simuls,["end"]) simuls[get-name(clk(c))] = my-clk-simuls @@ -213,7 +213,7 @@ defn emit-module (m:InModule) : simuls[get-name(clk(s))] = my-clk-simuls (c:StopStmt) : val my-clk-simuls = get?(simuls,get-name(clk(c)),Vector<Streamable>()) - add(my-clk-simuls,["$fdisplay(STDERR," ret(c) ");"]) + add(my-clk-simuls,["$fdisplay(STDERR,\"" ret(c) "\");"]) add(my-clk-simuls,["$finish;"]) simuls[get-name(clk(c))] = my-clk-simuls (s:Connect) : |