From 1d63b78f41ab3c3de88a5bb167f7412186dd677a Mon Sep 17 00:00:00 2001
From: azidar
Date: Fri, 11 Dec 2015 12:40:32 -0800
Subject: Stop now emits correct verilog to stop simulation, required passing a
 string not and integer

---
 src/main/stanza/verilog.stanza | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index 7196fe82..15c6ac6a 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -203,7 +203,7 @@ defn emit-module (m:InModule) :
                (c:StopStmt) : 
                   val my-clk-simuls = get?(simuls,get-name(clk(c)),Vector<Streamable>())
                   add(my-clk-simuls,["if(" emit(pred(s)) ") begin"])
-                  add(my-clk-simuls,["  $fdisplay(STDERR," ret(c) ");"])
+                  add(my-clk-simuls,["  $fdisplay(STDERR,\"" ret(c) "\");"])
                   add(my-clk-simuls,["  $finish;"])
                   add(my-clk-simuls,["end"])
                   simuls[get-name(clk(c))] = my-clk-simuls
@@ -213,7 +213,7 @@ defn emit-module (m:InModule) :
             simuls[get-name(clk(s))] = my-clk-simuls
          (c:StopStmt) : 
             val my-clk-simuls = get?(simuls,get-name(clk(c)),Vector<Streamable>())
-            add(my-clk-simuls,["$fdisplay(STDERR," ret(c) ");"])
+            add(my-clk-simuls,["$fdisplay(STDERR,\"" ret(c) "\");"])
             add(my-clk-simuls,["$finish;"])
             simuls[get-name(clk(c))] = my-clk-simuls
          (s:Connect) : 
-- 
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