diff options
| author | azidar | 2015-12-11 12:31:00 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 11:45:00 -0800 |
| commit | e562ef9773d5c9e368878a01c53b168fde36e9a0 (patch) | |
| tree | b181a9dbddec0c9845c9742025bc3f22f484be88 /src | |
| parent | fd35220712129f5f0074444008702af4aaf19ad2 (diff) | |
Fixed bug in printf and stop to correctly print to STDERR
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/stanza/verilog.stanza | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index de11229d..7196fe82 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -197,23 +197,23 @@ defn emit-module (m:InModule) : (c:PrintfStmt) : val my-clk-simuls = get?(simuls,get-name(clk(c)),Vector<Streamable>()) add(my-clk-simuls,["if(" emit(pred(s)) ") begin"]) - add(my-clk-simuls,[" $fdisplay(32/'h80000002," string-join(List(escape(string(c)),map(emit,args(c))), ", ") ");"]) + add(my-clk-simuls,[" $fdisplay(STDERR," string-join(List(escape(string(c)),map(emit,args(c))), ", ") ");"]) add(my-clk-simuls,["end"]) simuls[get-name(clk(c))] = my-clk-simuls (c:StopStmt) : val my-clk-simuls = get?(simuls,get-name(clk(c)),Vector<Streamable>()) add(my-clk-simuls,["if(" emit(pred(s)) ") begin"]) - add(my-clk-simuls,[" $fdisplay(32/'h80000002," ret(c) ");"]) + add(my-clk-simuls,[" $fdisplay(STDERR," ret(c) ");"]) add(my-clk-simuls,[" $finish;"]) add(my-clk-simuls,["end"]) simuls[get-name(clk(c))] = my-clk-simuls (s:PrintfStmt) : val my-clk-simuls = get?(simuls,get-name(clk(s)),Vector<Streamable>()) - add(my-clk-simuls,["$fdisplay(32/'h80000002," string-join(List(escape(string(s)),map(emit,args(s))), ", ") ");"]) + add(my-clk-simuls,["$fdisplay(STDERR," string-join(List(escape(string(s)),map(emit,args(s))), ", ") ");"]) simuls[get-name(clk(s))] = my-clk-simuls (c:StopStmt) : val my-clk-simuls = get?(simuls,get-name(clk(c)),Vector<Streamable>()) - add(my-clk-simuls,["$fdisplay(32/'h80000002," ret(c) ");"]) + add(my-clk-simuls,["$fdisplay(STDERR," ret(c) ");"]) add(my-clk-simuls,["$finish;"]) simuls[get-name(clk(c))] = my-clk-simuls (s:Connect) : @@ -307,6 +307,7 @@ defn emit-module (m:InModule) : updates[get-name(clock(mem-declaration))] = my-clk-update ;==== Actually printing module ===== + if length(simuls) != 0 : print-all(["integer STDERR = 32'h80000002;\n"]) val port-indent = " " print-all(["module " name(m) "(\n"]) for (p in ports(m),i in 1 to false) do : |