WIP, need to update chirrtl with new mask syntax

6 files changed, 73 insertions, 31 deletions

diff --git a/src/main/stanza/chirrtl.stanza b/src/main/stanza/chirrtl.stanza
index 58656118..049d0b0d 100644
--- a/src/main/stanza/chirrtl.stanza
+++ b/src/main/stanza/chirrtl.stanza
@@ -20,6 +20,7 @@ defstruct DataRef :
    exp : Expression
    male : Symbol
    female : Symbol
+   mask : Symbol
 
 public definterface Gender
 public val MALE = new Gender
@@ -41,6 +42,7 @@ defn to-ir (c:Circuit) :
       val sh = get-sym-hash(m,keys(v-keywords))
       val repl = HashTable<Symbol,DataRef>(symbol-hash)
       val ut = UnknownType()
+      val mport-types = HashTable<Symbol,Type>(symbol-hash)
       defn EMPs () -> MPorts : 
          MPorts(Vector<MPort>(),Vector<MPort>(),Vector<MPort>())
       defn collect-mports (s:Stmt) -> Stmt :
@@ -57,6 +59,7 @@ defn to-ir (c:Circuit) :
       defn collect-refs (s:Stmt) -> Stmt :
          match(s) :
             (s:CDefMemory) :
+               mport-types[name(s)] = type(s)
                val stmts = Vector<Stmt>()
                val naddr = firrtl-gensym(`GEN,sh)
                val taddr = UIntType(IntWidth(max(1,ceil-log2(size(s)))))
@@ -97,23 +100,24 @@ defn to-ir (c:Circuit) :
                val mem = DefMemory(info(s),name(s),type(s),size(s),1,read-l,map(name,rds),map(name,wrs),map(name,rws))
                Begin $ List(mem,to-list(stmts))
             (s:CDefMPort) :
+               mport-types[name(s)] = mport-types[mem(s)]
                val addrs = Vector<Symbol>()
                val ens = Vector<Symbol>()
                val masks = Vector<Symbol>()
                switch { _ == direction(s) } :
                   MReadWrite : 
-                     repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`wdata,`rdata)
+                     repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`wdata,`rdata,`wmask)
                      add(addrs,`addr)
                      add(ens,`wen)
                      add(ens,`ren)
                      add(masks,`wmask)
                   MWrite :
-                     repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`data,`data)
+                     repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`data,`data,`mask)
                      add(addrs,`addr)
                      add(ens,`en)
                      add(masks,`mask)
-                  else : ; TODO add MWrite for mask
-                     repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`data,`data)
+                  else :
+                     repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`data,`data,`blah)
                      add(addrs,`addr)
                      add(ens,`en)
 
@@ -126,26 +130,54 @@ defn to-ir (c:Circuit) :
                   add(stmts,Connect(info(s),SubField(SubField(Ref(mem(s),ut),name(s),ut),x,ut),exps(s)[2]))
                Begin $ to-list $ stmts   
             (s) : map(collect-refs,s)
-      defn to-ir-e (e:Expression,g:Gender) -> Expression :
-         match(map(to-ir-e{_,g},e)) :
-            (e:Ref) : 
-               if key?(repl,name(e)) : 
-                  val vt = repl[name(e)]
-                  switch {g == _ }:
-                     MALE : SubField(exp(vt),male(vt),ut)
-                     FEMALE : SubField(exp(vt),female(vt),ut)
-               else : e
-            (e) : e
       defn to-ir-s (s:Stmt) -> Stmt :
+         var has-write-mport? = false
+         defn to-ir-e (e:Expression,g:Gender) -> Expression :
+            match(map(to-ir-e{_,g},e)) :
+               (e:Ref) : 
+                  if key?(repl,name(e)) : 
+                     val vt = repl[name(e)]
+                     switch {g == _ }:
+                        MALE : SubField(exp(vt),male(vt),type(e))
+                        FEMALE : 
+                           has-write-mport? = true
+                           SubField(exp(vt),female(vt),type(e))
+                  else : e
+               (e) : e
+         defn get-mask (e:Expression) -> Expression :
+            match(map(get-mask,e)) :
+               (e:Ref) :
+                  if key?(repl,name(e)) : 
+                     val vt = repl[name(e)]
+                     val f = create-mask(`blah,mport-types[name(e)])
+                     SubField(exp(vt),mask(vt),type(f))
+                  else : e
+               (e) : e
          match(s) :
             (s:Connect) : 
-               val loc* = to-ir-e(loc(s),FEMALE)
+               val stmts = Vector<Stmt>()
                val roc* = to-ir-e(exp(s),MALE)
-               Connect(info(s),loc*,roc*)
+               val loc* = to-ir-e(loc(s),FEMALE)
+               add(stmts,Connect(info(s),loc*,roc*))
+               if has-write-mport? :
+                  val e = get-mask(loc(s))
+                  for x in create-exps(e) do :
+                     add(stmts,Connect(info(s),x,UInt(1)))
+               if length(stmts > 1) : Begin(to-list(stmts))
+               else : stmts[0]
             (s:BulkConnect) : 
+               val stmts = Vector<Stmt>()
                val loc* = to-ir-e(loc(s),FEMALE)
                val roc* = to-ir-e(exp(s),MALE)
-               BulkConnect(info(s),loc*,roc*)
+               add(stmts,BulkConnect(info(s),loc*,roc*))
+               if has-write-mport? :
+                  val ls = get-valid-points(type(loc(s)),type(exp(s)),DEFAULT,DEFAULT)
+                  val locs = create-exps(get-mask(loc(s)))
+                  for x in ls do :
+                     val loc* = locs[x[0]]
+                     add(stmts,Connect(info(s),loc*,UInt(1)))
+               if length(stmts > 1) : Begin(to-list(stmts))
+               else : stmts[0]
             (s) : map(to-ir-e{_,MALE}, map(to-ir-s,s))
       collect-mports(body(m))
       val s* = collect-refs(body(m))
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index de775648..4878dce5 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -50,6 +50,7 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
       ;RemoveSpecialChars()     
       ;TempElimination()                 ; Needs to check number of uses
       ;===============
+      InferTypes()
       ToIR()            
       ;===============
       CheckHighForm()          
diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza
index 97660b46..67dfef8d 100644
--- a/src/main/stanza/errors.stanza
+++ b/src/main/stanza/errors.stanza
@@ -654,11 +654,18 @@ public defn check-genders (c:Circuit) -> Circuit :
    defn check-gender (info:FileInfo,genders:HashTable<Symbol,Gender>,e:Expression,desired:Gender) -> False :
       val gender = get-gender(e,genders)
       val kind* = get-kind(e)
-      val flip? = 
-         match(type(e)) :
-            (t:BundleType) : 
-               for f in fields(t) any? : flip(f) == REVERSE
-            (t) : false
+      defn flip? (t:Type) -> True|False :
+         var f? = false
+         defn flip-rec (t:Type,f:Flip) -> Type :
+            match(t) :
+               (t:BundleType) : 
+                  for field in fields(t) do : 
+                     flip-rec(type(field),f * flip(field))
+               (t:VectorType) : flip-rec(type(t),f)
+               (t) : if f == REVERSE : f? = true
+            t
+         flip-rec(t,DEFAULT)
+      val has-flip? = flip?(t)
          
       ;println(e)
       ;println(gender)
@@ -670,7 +677,7 @@ public defn check-genders (c:Circuit) -> Circuit :
          [MALE, FEMALE] : 
             add(errors,WrongGender(info,to-symbol(e),as-srcsnk(desired),as-srcsnk(gender)))
          [FEMALE, MALE] : 
-            if (kind* == PortKind() or kind* == InstanceKind()) and flip? == false : 
+            if (kind* == PortKind() or kind* == InstanceKind()) and has-flip? == false : 
                ; OK!
                false
             else : 
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index fa103fe3..d891227f 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -265,10 +265,10 @@ defsyntax firrtl :
 
       stmt = (read mport ?name:#id! #=! ?mem:#id! (@get ?index:#exp!) ?clk:#exp!) :
          CDefMPort(first-info(form),name,mem,list(index,clk),MRead)
-      stmt = (write mport ?name:#id! #=! ?mem:#id! (@get ?index:#exp!) ?clk:#exp! ?mask:#exp!) :
-         CDefMPort(first-info(form),name,mem,list(index,clk,mask),MWrite)
-      stmt = (rdwr mport ?name:#id! #=! ?mem:#id! (@get ?index:#exp!) ?clk:#exp! ?mask:#exp!) :
-         CDefMPort(first-info(form),name,mem,list(index,clk,mask),MReadWrite)
+      stmt = (write mport ?name:#id! #=! ?mem:#id! (@get ?index:#exp!) ?clk:#exp!) :
+         CDefMPort(first-info(form),name,mem,list(index,clk),MWrite)
+      stmt = (rdwr mport ?name:#id! #=! ?mem:#id! (@get ?index:#exp!) ?clk:#exp!) :
+         CDefMPort(first-info(form),name,mem,list(index,clk),MReadWrite)
 
       stmt = (mem ?name:#id! #:! (?ms:#mstat ...)) :
          defn grab (f:MStat -> True|False) :
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index 7a9cff31..2f4bf973 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -356,10 +356,7 @@ defmethod print (o:OutputStream, c:Stmt) :
          else :
             print-all(o, ["cmem " name(c) " : " type(c) "[" size(c) "]"])
       (c:CDefMPort) :
-         if direction(c) == MRead : 
-            print-all(o, [direction(c) " mport " name(c) " = " mem(c) "[" exps(c)[0] "], " exps(c)[1]])
-         else : 
-            print-all(o, [direction(c) " mport " name(c) " = " mem(c) "[" exps(c)[0] "], " exps(c)[1] ", " exps(c)[2]])
+         print-all(o, [direction(c) " mport " name(c) " = " mem(c) "[" exps(c)[0] "], " exps(c)[1]])
 
    if not c typeof Conditionally|Begin|Empty: print-debug(o,c)
 
@@ -469,6 +466,7 @@ defmethod map (f: Expression -> Expression, c:Stmt) -> Stmt :
       (c:BulkConnect) : BulkConnect(info(c),f(loc(c)), f(exp(c)))
       (c:Stop) : Stop(info(c),ret(c),f(clk(c)),f(en(c)))
       (c:Print) : Print(info(c),string(c),map(f,args(c)),f(clk(c)),f(en(c)))
+      (c:CDefMPort) : CDefMPort(info(c),name(c), mem(c), f(clock(c)), f(reset(c)), f(init(c)))
       (c) : c
 
 public defmulti map<?T> (f: Stmt -> Stmt, c:?T&Stmt) -> T
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index a5d72ba4..4f40c8b7 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -713,6 +713,10 @@ defn infer-types (c:Circuit) -> Circuit :
       val types = HashTable<Symbol,Type>(symbol-hash)
       defn infer-types-e (e:Expression) -> Expression :
          match(map(infer-types-e,e)) :
+            (e:Ref) : Ref(name(e), types[name(e)])
+            (e:SubField) : SubField(exp(e),name(e),field-type(type(exp(e)),name(e)))
+            (e:SubIndex) : SubIndex(exp(e),value(e),sub-type(type(exp(e))))
+            (e:SubAccess) : SubAccess(exp(e),index(e),sub-type(type(exp(e))))
             (e:WRef) : WRef(name(e), types[name(e)],kind(e),gender(e))
             (e:WSubField) : WSubField(exp(e),name(e),field-type(type(exp(e)),name(e)),gender(e))
             (e:WSubIndex) : WSubIndex(exp(e),value(e),sub-type(type(exp(e))),gender(e))