diff options
| author | azidar | 2016-01-15 17:00:26 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:18 -0800 |
| commit | 073a2cc49a77b877021a0d460c873e1a91e9af89 (patch) | |
| tree | eb7088ac64de1d62a7ef0def27f46c10a8e27a9b /src | |
| parent | a5c850beb0568c09b581f925aa5ca3bf561ac974 (diff) | |
Verilog emission no longer casts input to shr or bit select
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/stanza/passes.stanza | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index fea1a033..4c305814 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -2383,7 +2383,7 @@ defn op-stream (doprim:DoPrim) -> Streamable : (t:SIntType) : [cast(a0()) " >>> " a1()] (t) : [cast(a0()) " >> " a1()] SHIFT-LEFT-OP : [cast(a0()) " << " c0()] - SHIFT-RIGHT-OP : [cast(a0()) "[" long!(type(a0())) - to-long(1) ":" c0() "]"] + SHIFT-RIGHT-OP : [a0() "[" long!(type(a0())) - to-long(1) ":" c0() "]"] NEG-OP : ["-{" cast(a0()) "}"] CONVERT-OP : match(type(a0())) : @@ -2394,8 +2394,8 @@ defn op-stream (doprim:DoPrim) -> Streamable : BIT-OR-OP : [cast(a0()) " | " cast(a1())] BIT-XOR-OP : [cast(a0()) " ^ " cast(a1())] CONCAT-OP : ["{" cast(a0()) "," cast(a1()) "}"] - BIT-SELECT-OP : [cast(a0()) "[" c0() "]"] - BITS-SELECT-OP : [cast(a0()) "[" c0() ":" c1() "]"] + BIT-SELECT-OP : [a0() "[" c0() "]"] + BITS-SELECT-OP : [a0() "[" c0() ":" c1() "]"] BIT-AND-REDUCE-OP : val v = Vector<Streamable>() for b in 0 to to-int(long!(type(doprim))) do : |