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authorazidar2016-01-16 15:47:37 -0800
committerazidar2016-01-16 15:47:37 -0800
commitdf1bb3aced1e560dd919460a846c28ad2deacbd3 (patch)
tree29a8d7d726acf9ad810c262e6e8228d3346c441a /src
parentc4271d9e428bba7b447ed6d18fb11729d2b61b22 (diff)
Standard Verilog doesn't use Resolve(), but lists out the resolution passes individually
Diffstat (limited to 'src')
-rw-r--r--src/main/stanza/compilers.stanza21
-rw-r--r--src/main/stanza/passes.stanza3
2 files changed, 13 insertions, 11 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index cfc7824b..de775648 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -56,15 +56,13 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
;===============
ToWorkingIR()
;===============
- ResolveKinds()
- InferTypes()
- CheckTypes()
- ResolveGenders()
- CheckGenders()
- InferWidths()
- CheckWidths()
- ;===============
- Resolve()
+ ResolveKinds()
+ InferTypes()
+ CheckTypes()
+ ResolveGenders()
+ CheckGenders()
+ InferWidths()
+ CheckWidths()
;===============
ExpandConnects()
;===============
@@ -96,12 +94,14 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
InferWidths()
CheckWidths()
;===============
+ Verilog(with-output(c))
+ ;===============
;ToRealIR()
;Pad()
;CheckWidths()
;CheckHighForm()
;CheckLowForm()
- Verilog(with-output(c))
+ ;Verilog(with-output(c))
]
public defstruct StandardFIRRTL <: Compiler :
@@ -114,7 +114,6 @@ public defmethod passes (c:StandardFIRRTL) -> List<Pass> :
FIRRTL(with-output(c))
]
-
public defstruct StandardLoFIRRTL <: Compiler :
with-output : (() -> False) -> False with: (as-method => true)
public defmethod backend (c:StandardLoFIRRTL) -> List<Pass> :
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 45aaf755..a5d72ba4 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -1642,8 +1642,11 @@ public defmethod name (b:Resolve) -> String : "Resolve"
public defmethod short-name (b:Resolve) -> String : "resolve"
defn resolve (c:Circuit) -> Circuit :
+ check-width $
infer-widths $
+ check-genders $
resolve-genders $
+ check-types $
infer-types $
resolve-kinds $ c