diff options
| author | azidar | 2016-01-15 16:13:41 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 11:45:00 -0800 |
| commit | 23e017855e76fd0dad7af10029250ab33bd6f7e3 (patch) | |
| tree | 76aeab658a1653dc68a647a0455703438dc45750 /src | |
| parent | 1f4bbf566ac5b9b01b3fdb18e5a33103b3182d01 (diff) | |
Printf no longer adds a new line
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/stanza/verilog.stanza | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index 6b51f390..b5196dac 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -197,7 +197,7 @@ defn emit-module (m:InModule) : (c:PrintfStmt) : val my-clk-simuls = get?(simuls,get-name(clk(c)),Vector<Streamable>()) add(my-clk-simuls,["if(" emit(pred(s)) ") begin"]) - add(my-clk-simuls,[" $fdisplay(STDERR," string-join(List(escape(string(c)),map(emit,args(c))), ", ") ");"]) + add(my-clk-simuls,[" $fwrite(STDERR," string-join(List(escape(string(c)),map(emit,args(c))), ", ") ");"]) add(my-clk-simuls,["end"]) simuls[get-name(clk(c))] = my-clk-simuls (c:StopStmt) : @@ -209,7 +209,7 @@ defn emit-module (m:InModule) : simuls[get-name(clk(c))] = my-clk-simuls (s:PrintfStmt) : val my-clk-simuls = get?(simuls,get-name(clk(s)),Vector<Streamable>()) - add(my-clk-simuls,["$fdisplay(STDERR," string-join(List(escape(string(s)),map(emit,args(s))), ", ") ");"]) + add(my-clk-simuls,["$fwrite(STDERR," string-join(List(escape(string(s)),map(emit,args(s))), ", ") ");"]) simuls[get-name(clk(s))] = my-clk-simuls (c:StopStmt) : val my-clk-simuls = get?(simuls,get-name(clk(c)),Vector<Streamable>()) |