From 23e017855e76fd0dad7af10029250ab33bd6f7e3 Mon Sep 17 00:00:00 2001 From: azidar Date: Fri, 15 Jan 2016 16:13:41 -0800 Subject: Printf no longer adds a new line --- src/main/stanza/verilog.stanza | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index 6b51f390..b5196dac 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -197,7 +197,7 @@ defn emit-module (m:InModule) : (c:PrintfStmt) : val my-clk-simuls = get?(simuls,get-name(clk(c)),Vector()) add(my-clk-simuls,["if(" emit(pred(s)) ") begin"]) - add(my-clk-simuls,[" $fdisplay(STDERR," string-join(List(escape(string(c)),map(emit,args(c))), ", ") ");"]) + add(my-clk-simuls,[" $fwrite(STDERR," string-join(List(escape(string(c)),map(emit,args(c))), ", ") ");"]) add(my-clk-simuls,["end"]) simuls[get-name(clk(c))] = my-clk-simuls (c:StopStmt) : @@ -209,7 +209,7 @@ defn emit-module (m:InModule) : simuls[get-name(clk(c))] = my-clk-simuls (s:PrintfStmt) : val my-clk-simuls = get?(simuls,get-name(clk(s)),Vector()) - add(my-clk-simuls,["$fdisplay(STDERR," string-join(List(escape(string(s)),map(emit,args(s))), ", ") ");"]) + add(my-clk-simuls,["$fwrite(STDERR," string-join(List(escape(string(s)),map(emit,args(s))), ", ") ");"]) simuls[get-name(clk(s))] = my-clk-simuls (c:StopStmt) : val my-clk-simuls = get?(simuls,get-name(clk(c)),Vector()) -- cgit v1.2.3