diff options
| author | azidar | 2016-01-15 17:00:52 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:18 -0800 |
| commit | 1c610defbc443c45a5bf02cc419d4954a798ca31 (patch) | |
| tree | d0ffaa301589af6f0592bec629970de3849c9c8e /src | |
| parent | 073a2cc49a77b877021a0d460c873e1a91e9af89 (diff) | |
printf no longer includes a new line
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/stanza/passes.stanza | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 4c305814..51564f95 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -2485,7 +2485,7 @@ defn emit-verilog (m:InModule) -> Module : ["$fdisplay(32/'h80000002," ret ");$finish;"] defn printf (str:String,args:List<Expression>) -> Streamable : val str* = join(List(escape(str),args),",") - ["$fdisplay(32/'h80000002," str* ");"] + ["$fwrite(32/'h80000002," str* ");"] defn delay (e:Expression, n:Int, clk:Expression) -> Expression : var e* = e for i in 0 to n do : |