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-rw-r--r--src/main/stanza/passes.stanza2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 4c305814..51564f95 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -2485,7 +2485,7 @@ defn emit-verilog (m:InModule) -> Module :
["$fdisplay(32/'h80000002," ret ");$finish;"]
defn printf (str:String,args:List<Expression>) -> Streamable :
val str* = join(List(escape(str),args),",")
- ["$fdisplay(32/'h80000002," str* ");"]
+ ["$fwrite(32/'h80000002," str* ");"]
defn delay (e:Expression, n:Int, clk:Expression) -> Expression :
var e* = e
for i in 0 to n do :