aboutsummaryrefslogtreecommitdiff
path: root/test
AgeCommit message (Expand)Author
2015-10-01Merge pull request #43 from ucb-bar/new-semanticsAndrew Waterman
2015-10-01Merge pull request #41 from ucb-bar/fix-init-accessorAndrew Waterman
2015-10-01Change of FIRRTL semantics!azidar
2015-10-01Updated tests for previous change that removed RemoveScope test from the Stan...azidar
2015-09-30Make Link.fir reference relative path, so it doesn't need someone's particula...ducky
2015-09-30Fixed test so it passes, as it shouldazidar
2015-09-30Made simple9.fir a short, more isolated test caseazidar
2015-09-30Moved To-Real-Ir earlier, so CheckWidth could happen before PadWidthazidar
2015-09-30Fixed naming bug where __1 was matching. Caused lots o issues.azidar
2015-09-29Fixed final bug. All tests pass. Accessors are a go.azidar
2015-09-29Added DecToIndexer/DecFromIndexer. Fixed most use cases of incorrect catching...azidar
2015-09-24Updated conditional read exampleazidar
2015-09-01Added a conditional readport example, with new idea of representing a read en...azidar
2015-08-28Moved check type and check kind after check genderazidar
2015-08-26Fixed bug where firrtl was incorrectly judging the width of a bigint. #36 #37.azidar
2015-08-25Fixed bug in split expression that leaked connect statements out of a conditi...azidar
2015-08-25Added width check pass with tests. #22.azidar
2015-08-24Changed all tests to use verilog backend.azidar
2015-08-24Removed old chisel3 tests that all failed for syntax reasons. Tests should no...azidar
2015-08-20Added tests, cleaned up repoazidar
2015-08-20Added Poison node. Includes tests. #26.azidar
2015-08-20Added rsh test for const-propazidar
2015-08-19Added new const propagation testazidar
2015-08-19Fixed width inference bug where constraints were propagating backwards.azidar
2015-08-18Updated shr test so it is an expected passazidar
2015-08-18Fixed so its length is greater than what it connects to. Changed shr to be e...azidar
2015-08-17Removed leading zeros from UInt constantsazidar
2015-08-17Fixed bug where equality between expressions was incorrect, leading toazidar
2015-08-17Added tests for shl and mem. Fixed bug in verilog output of mem size.azidar
2015-08-04Added check for reading from outputs with flipsazidar
2015-08-04Added verilog keywords to uniquify themazidar
2015-08-04Fixed reading from instance's input ports. Fixed unique naming bug.azidar
2015-08-03Changed name mangling to use _ as a delin. Fixed bug in checking forazidar
2015-08-03Fixed performance bug in Split Expressions. Changed delin for connect indexed...azidar
2015-07-31Reading from output ports no longer causes errorsazidar
2015-07-31Added errors for bulk connects where field names match but types/flips don'tazidar
2015-07-31Updated tests to pipe from stderr to stdoutazidar
2015-07-30Added module name to error messages.azidar
2015-07-30Updated error and feature tests. Fixed bug in detecting incorrect gendersazidar
2015-07-30Added eqv for bitwise equality, and change eq to be arithmetic equalityazidar
2015-07-30Updated lots of tests so they pass. Found one bug in expand whensazidar
2015-07-29Finished supporting Chisel 2.0 Ref ChipAdam Izraelevitz
2015-07-29Add bigint support.Adam Izraelevitz
2015-07-28Integrated bigint. Mostly works, but getting "cast" error for make Test.Adam Izraelevitz
2015-07-14Added tests for clocks. Added remove scope and special chars passes. Added te...azidar
2015-07-14Added clock supportazidar
2015-07-14Pass most tests. The ones that do not pass are not expected to, yetazidar
2015-07-14Added chisel feedback to firrtl spec. Datapath_new triggers too large a width...azidar
2015-07-14Still partial commit, many tests pass. Many tests fail.azidar
2015-07-14In progress commitazidar