diff options
| author | azidar | 2015-08-03 11:51:50 -0700 |
|---|---|---|
| committer | azidar | 2015-08-03 11:51:50 -0700 |
| commit | 6f098fb5328ebfe3137ff449e9905bdf0f668859 (patch) | |
| tree | 92c5386f1696920dd9667ffa96f442fce1c44c3c /test | |
| parent | 342e7760582280d6106a57891d9ea3374551bf77 (diff) | |
Fixed performance bug in Split Expressions. Changed delin for connect indexed. Fixed various broken tests.
Diffstat (limited to 'test')
| -rw-r--r-- | test/errors/gender/BulkWrong.fir | 6 | ||||
| -rw-r--r-- | test/passes/expand-connect-indexed/bundle-vecs.fir | 10 | ||||
| -rw-r--r-- | test/passes/infer-types/primops.fir | 27 |
3 files changed, 29 insertions, 14 deletions
diff --git a/test/errors/gender/BulkWrong.fir b/test/errors/gender/BulkWrong.fir index 632dd709..e2dda086 100644 --- a/test/errors/gender/BulkWrong.fir +++ b/test/errors/gender/BulkWrong.fir @@ -6,9 +6,11 @@ circuit BTB : input clk : Clock input reset : UInt<1> input req : {valid : UInt<1>, bits : {addr : UInt<39>}} - output r : UInt<1> - wire x : {valid : UInt<1>, bits : {addr : UInt<39>}} + output r : { x : UInt<1>, flip y : UInt<1>} + wire x : {valid : UInt<1>, bits : {addr : UInt<39>}} req <> x + + wire z : {x : UInt<1>, flip y : UInt<1> } x.valid := r diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir index 7fc3a6e5..e094abcc 100644 --- a/test/passes/expand-connect-indexed/bundle-vecs.fir +++ b/test/passes/expand-connect-indexed/bundle-vecs.fir @@ -23,11 +23,11 @@ circuit top : ; CHECK: wire b{{[_$]+}}x : UInt<32> ; CHECK: wire b{{[_$]+}}y : UInt<32> ; CHECK: b{{[_$]+}}x := a{{[_$]+}}0{{[_$]+}}x - ; CHECK: node i!0 = i - ; CHECK: when eqv(i!0, UInt("h00000001")) : b{{[_$]+}}x := a{{[_$]+}}1{{[_$]+}}x - ; CHECK: node i!1 = i - ; CHECK: when eqv(i!1, UInt("h00000000")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y - ; CHECK: when eqv(i!1, UInt("h00000001")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y + ; CHECK: node i*0 = i + ; CHECK: when eqv(i*0, UInt("h00000001")) : b{{[_$]+}}x := a{{[_$]+}}1{{[_$]+}}x + ; CHECK: node i*1 = i + ; CHECK: when eqv(i*1, UInt("h00000000")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y + ; CHECK: when eqv(i*1, UInt("h00000001")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y j := b.x b.y := UInt(1) diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir index e12a41af..89c06e7e 100644 --- a/test/passes/infer-types/primops.fir +++ b/test/passes/infer-types/primops.fir @@ -143,16 +143,29 @@ circuit top : node wcvt = cvt(a) ;CHECK: node wcvt = cvt(a@<t:UInt>)@<t:SInt> node zcvt = cvt(c) ;CHECK: node zcvt = cvt(c@<t:SInt>)@<t:SInt> - node vneg = neg(a) ;CHECK: node vneg = neg(a@<t:UInt>)@<t:UInt> - node wneg = neg(a) ;CHECK: node wneg = neg(a@<t:UInt>)@<t:UInt> - node zneg = neg(c) ;CHECK: node zneg = neg(c@<t:SInt>)@<t:UInt> + node vneg = neg(a) ;CHECK: node vneg = neg(a@<t:UInt>)@<t:SInt> + node wneg = neg(a) ;CHECK: node wneg = neg(a@<t:UInt>)@<t:SInt> + node zneg = neg(c) ;CHECK: node zneg = neg(c@<t:SInt>)@<t:SInt> - node uand = and(a, b) ;CHECK: node uand = and(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node vor = or(a, b) ;CHECK: node vor = or(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node wnot = not(a) ;CHECK: node wnot = not(a@<t:UInt>)@<t:UInt> + node unot = not(c) ;CHECK: node unot = not(c@<t:SInt>)@<t:SInt> + + node wand = and(a, b) ;CHECK: node wand = and(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node uand = and(c, d) ;CHECK: node uand = and(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node wor = or(a, b) ;CHECK: node wor = or(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node uor = or(c, d) ;CHECK: node uor = or(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + node wxor = xor(a, b) ;CHECK: node wxor = xor(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node uxor = xor(c, d) ;CHECK: node uxor = xor(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node wbit = bit(a, 0) ;CHECK: node wbit = bit(a@<t:UInt>, 0)@<t:UInt> + node ubit = bit(c, 0) ;CHECK: node ubit = bit(c@<t:SInt>, 0)@<t:UInt> + + node wbits = bits(a, 2, 0) ;CHECK: node wbits = bits(a@<t:UInt>, 2, 0)@<t:UInt> + node ubits = bits(c, 2, 0) ;CHECK: node ubits = bits(c@<t:SInt>, 2, 0)@<t:UInt> + node xcat = cat(a, b) ;CHECK: node xcat = cat(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node ybit = bit(a, 0) ;CHECK: node ybit = bit(a@<t:UInt>, 0)@<t:UInt> - node zbits = bits(a, 2, 0) ;CHECK: node zbits = bits(a@<t:UInt>, 2, 0)@<t:UInt> node uandr = andr(a, b, a) ;CHECK: node uandr = andr(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt> node uorr = orr(a, b, a) ;CHECK: node uorr = orr(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt> |
