Fixed performance bug in Split Expressions. Changed delin for connect indexed. Fixed various broken tests.

7 files changed, 67 insertions, 42 deletions

diff --git a/TODO b/TODO
index 030634d4..4a85bd79 100644
--- a/TODO
+++ b/TODO
@@ -9,6 +9,7 @@ add clock check to high firrtl check
 registers in onreset cannot have flips
 add equivalence to spec
 remove SInt from bit/bits in spec
+naming still doesn't work - x!0 will conflict with x
 
 Tests:
    Lowering for instance types with bundle ports
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index 8de688d7..79057791 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -11,6 +11,7 @@ public val bundle-expand-delin = `$
 public val module-expand-delin = `$
 public val scope-delin = `%
 public val temp-delin = `!
+public val sub-delin = `*
 public val inline-delin = `^
 
 public definterface PortDirection
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index 7bb7ff01..f3fb5a53 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -10,22 +10,27 @@ public defmulti print-debug (o:OutputStream, e:Expression|Stmt|Type|Port|Field|M
 ;============== GENSYM STUFF ======================
 
 
-public defn firrtl-gensym (s:Symbol) -> Symbol : firrtl-gensym(s,HashTable<Symbol,Int>(symbol-hash))
-
+public defn firrtl-gensym (s:Symbol) -> Symbol :
+   firrtl-gensym(s,HashTable<Symbol,Int>(symbol-hash))
 public defn firrtl-gensym (s:Symbol,sym-hash:HashTable<Symbol,Int>) -> Symbol :
-   defn get-new (s:Symbol, i:Int) -> Symbol :
-      val s* = symbol-join([s i])
-      if key?(sym-hash,s*) :
-         get-new(s,i + 1)
-      else :
-         sym-hash[s] = i
-         sym-hash[s*] = 0
-         s*
-   get-new(s,0)
-   
+   firrtl-gensym(s,sym-hash,temp-delin)
 public defn firrtl-gensym (sym-hash:HashTable<Symbol,Int>) -> Symbol :
    firrtl-gensym(`gen,sym-hash)
 
+public defn firrtl-gensym (s:Symbol,sym-hash:HashTable<Symbol,Int>,delin:Symbol) -> Symbol :
+   val num = get?(sym-hash,s,0)
+   sym-hash[s] = num + 1
+   symbol-join([s delin num])
+   ;defn get-new (s:Symbol, i:Int) -> Symbol :
+   ;   val s* = symbol-join([s i])
+   ;   if key?(sym-hash,s*) :
+   ;      get-new(s,i + 1)
+   ;   else :
+   ;      sym-hash[s] = i
+   ;      sym-hash[s*] = 0
+   ;      s*
+   ;get-new(s,0)
+   
 public defn get-sym-hash (m:InModule) -> HashTable<Symbol,Int> :
    val sym-hash = HashTable<Symbol,Int>(symbol-hash)
    defn add-name (s:Symbol) -> False :
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index d5034f8a..4b99a4f8 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -1140,15 +1140,15 @@ defn expand-connect-indexed-stmt (s: Stmt,sh:HashTable<Symbol,Int>) -> Stmt :
       DoPrim(EQUIV-OP,list(e1,e2),List(),UIntType(UnknownWidth()))
    defn get-name (e:Expression) -> Symbol :
       match(e) :
-         (e:WRef) : symbol-join([name(e) temp-delin])
-         (e:WSubfield) : symbol-join([get-name(exp(e)) `. name(e) temp-delin])
-         (e:WIndex) : symbol-join([get-name(exp(e)) `. to-symbol(value(e)) temp-delin])
+         (e:WRef) : name(e)
+         (e:WSubfield) : symbol-join([get-name(exp(e)) `. name(e)])
+         (e:WIndex) : symbol-join([get-name(exp(e)) `. to-symbol(value(e))])
          (e) : `T
    match(s) :
       (s:ConnectToIndexed) : Begin $
          if length(locs(s)) == 0 : list(EmptyStmt())
          else :
-            val ref = WRef(firrtl-gensym(get-name(index(s)),sh),type(index(s)),NodeKind(),UNKNOWN-GENDER)
+            val ref = WRef(firrtl-gensym(get-name(index(s)),sh,sub-delin),type(index(s)),NodeKind(),UNKNOWN-GENDER)
             append(
                list(DefNode(info(s),name(ref),index(s)))
                to-list $
@@ -1162,7 +1162,7 @@ defn expand-connect-indexed-stmt (s: Stmt,sh:HashTable<Symbol,Int>) -> Stmt :
       (s:ConnectFromIndexed) : Begin $
          if length(exps(s)) == 0 : list(EmptyStmt())
          else :
-            val ref = WRef(firrtl-gensym(get-name(index(s)),sh),type(index(s)),NodeKind(),UNKNOWN-GENDER)
+            val ref = WRef(firrtl-gensym(get-name(index(s)),sh,sub-delin),type(index(s)),NodeKind(),UNKNOWN-GENDER)
             append(
                list(Connect(info(s),loc(s),head(exps(s))),DefNode(info(s),name(ref),index(s)))
                to-list $
@@ -2165,20 +2165,23 @@ defn full-name (e:Expression) -> Symbol|False :
 defn split-exp (c:Circuit) :
    defn split-exp-s (s:Stmt,v:Vector<Stmt>,sh:HashTable<Symbol,Int>) -> False :
       defn split-exp-e (e:Expression,n:Symbol|False,info:FileInfo) -> Expression :
-         match(map(split-exp-e{_,n,info},e)) :
+         match(e) :
             (e:DoPrim) : 
-               var all-same-type? = true
-               for x in args(e) do :
-                  if type(x) != type(e) : all-same-type? = false
-               all-same-type? = false
-               if not all-same-type? : 
+               ;var all-same-type? = true
+               ;for x in args(e) do :
+               ;   if type(x) != type(e) : all-same-type? = false
+               ;all-same-type? = false
+               ;if not all-same-type? : 
+                  ;val n* = 
+                  ;   if n typeof False : firrtl-gensym(`T,sh)
+                  ;   else : firrtl-gensym(symbol-join([n as Symbol temp-delin]),sh)
                   val n* = 
-                     if n typeof False : firrtl-gensym(`T,sh)
-                     else : firrtl-gensym(symbol-join([n as Symbol temp-delin]),sh)
-                  add(v,DefNode(info,n*,e))
+                     if n typeof False : firrtl-gensym(`T,sh,temp-delin)
+                     else : firrtl-gensym(n as Symbol,sh,temp-delin)
+                  add(v,DefNode(info,n*,map(split-exp-e{_,n,info},e)))
                   WRef(n*,type(e),NodeKind(),UNKNOWN-GENDER)
-               else : e
-            (e) : e
+               ;else : e
+            (e) : map(split-exp-e{_,n,info},e)
       defn f (s:Stmt) -> False: split-exp-s(s,v,sh)
       match(s) :
          (s:Begin) : 
diff --git a/test/errors/gender/BulkWrong.fir b/test/errors/gender/BulkWrong.fir
index 632dd709..e2dda086 100644
--- a/test/errors/gender/BulkWrong.fir
+++ b/test/errors/gender/BulkWrong.fir
@@ -6,9 +6,11 @@ circuit BTB :
     input clk : Clock
     input reset : UInt<1>
     input req : {valid : UInt<1>, bits : {addr : UInt<39>}}
-    output r : UInt<1>
 
-    wire x : {valid : UInt<1>, bits : {addr : UInt<39>}}
+    output r : { x : UInt<1>, flip y : UInt<1>}
 
+    wire x : {valid : UInt<1>, bits : {addr : UInt<39>}}
     req <> x
+
+    wire z : {x : UInt<1>, flip y : UInt<1> }
     x.valid := r
diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir
index 7fc3a6e5..e094abcc 100644
--- a/test/passes/expand-connect-indexed/bundle-vecs.fir
+++ b/test/passes/expand-connect-indexed/bundle-vecs.fir
@@ -23,11 +23,11 @@ circuit top :
       ; CHECK: wire b{{[_$]+}}x : UInt<32>
       ; CHECK: wire b{{[_$]+}}y : UInt<32>
       ; CHECK: b{{[_$]+}}x := a{{[_$]+}}0{{[_$]+}}x
-      ; CHECK: node i!0 = i
-      ; CHECK: when eqv(i!0, UInt("h00000001")) : b{{[_$]+}}x := a{{[_$]+}}1{{[_$]+}}x      
-      ; CHECK: node i!1 = i
-      ; CHECK: when eqv(i!1, UInt("h00000000")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y      
-      ; CHECK: when eqv(i!1, UInt("h00000001")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y      
+      ; CHECK: node i*0 = i
+      ; CHECK: when eqv(i*0, UInt("h00000001")) : b{{[_$]+}}x := a{{[_$]+}}1{{[_$]+}}x      
+      ; CHECK: node i*1 = i
+      ; CHECK: when eqv(i*1, UInt("h00000000")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y      
+      ; CHECK: when eqv(i*1, UInt("h00000001")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y      
       j := b.x
       b.y := UInt(1)
       
diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir
index e12a41af..89c06e7e 100644
--- a/test/passes/infer-types/primops.fir
+++ b/test/passes/infer-types/primops.fir
@@ -143,16 +143,29 @@ circuit top :
       node wcvt = cvt(a) ;CHECK: node wcvt = cvt(a@<t:UInt>)@<t:SInt>
       node zcvt = cvt(c) ;CHECK: node zcvt = cvt(c@<t:SInt>)@<t:SInt>
    
-      node vneg = neg(a)   ;CHECK: node vneg = neg(a@<t:UInt>)@<t:UInt>
-      node wneg = neg(a) ;CHECK: node wneg = neg(a@<t:UInt>)@<t:UInt>
-      node zneg = neg(c) ;CHECK: node zneg = neg(c@<t:SInt>)@<t:UInt>
+      node vneg = neg(a)   ;CHECK: node vneg = neg(a@<t:UInt>)@<t:SInt>
+      node wneg = neg(a) ;CHECK: node wneg = neg(a@<t:UInt>)@<t:SInt>
+      node zneg = neg(c) ;CHECK: node zneg = neg(c@<t:SInt>)@<t:SInt>
    
-      node uand = and(a, b) ;CHECK: node uand = and(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node vor = or(a, b)  ;CHECK: node vor = or(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node wnot = not(a) ;CHECK: node wnot = not(a@<t:UInt>)@<t:UInt>
+      node unot = not(c) ;CHECK: node unot = not(c@<t:SInt>)@<t:SInt>
+
+      node wand = and(a, b) ;CHECK: node wand = and(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node uand = and(c, d) ;CHECK: node uand = and(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
+
+      node wor = or(a, b)  ;CHECK: node wor = or(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node uor = or(c, d)  ;CHECK: node uor = or(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
+
       node wxor = xor(a, b) ;CHECK: node wxor = xor(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node uxor = xor(c, d) ;CHECK: node uxor = xor(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
+
+      node wbit = bit(a, 0) ;CHECK: node wbit = bit(a@<t:UInt>, 0)@<t:UInt>
+      node ubit = bit(c, 0) ;CHECK: node ubit = bit(c@<t:SInt>, 0)@<t:UInt>
+
+      node wbits = bits(a, 2, 0) ;CHECK: node wbits = bits(a@<t:UInt>, 2, 0)@<t:UInt>
+      node ubits = bits(c, 2, 0) ;CHECK: node ubits = bits(c@<t:SInt>, 2, 0)@<t:UInt>
+
       node xcat = cat(a, b) ;CHECK: node xcat = cat(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node ybit = bit(a, 0) ;CHECK: node ybit = bit(a@<t:UInt>, 0)@<t:UInt>
-      node zbits = bits(a, 2, 0) ;CHECK: node zbits = bits(a@<t:UInt>, 2, 0)@<t:UInt>
 
       node uandr = andr(a, b, a) ;CHECK: node uandr = andr(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt>
       node uorr = orr(a, b, a) ;CHECK: node uorr = orr(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt>