In progress commit

6 files changed, 114 insertions, 3 deletions

diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir
new file mode 100644
index 00000000..01347fdd
--- /dev/null
+++ b/test/passes/expand-whens/reg-dwc.fir
@@ -0,0 +1,21 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+circuit top :
+   module top :
+      wire p : UInt
+      p := UInt(1)
+      reg r : UInt
+      when p :
+         r := UInt(20)
+
+; CHECK: Expand Whens
+
+; CHECK: circuit top :
+; CHECK:   module top :
+; CHECK:     wire p : UInt
+; CHECK:     reg r : UInt
+; CHECK:     p := UInt(1)
+; CHECK:     when p : r := UInt(20)
+
+; CHECK: Finished Expand Whens
+
+
diff --git a/test/passes/expand-whens/reg-dwoc.fir b/test/passes/expand-whens/reg-dwoc.fir
new file mode 100644
index 00000000..521e1710
--- /dev/null
+++ b/test/passes/expand-whens/reg-dwoc.fir
@@ -0,0 +1,21 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+circuit top :
+   module top :
+      wire p : UInt
+      p := UInt(1)
+      reg r : UInt
+      when p :
+         on-reset r := UInt(10)
+         r := UInt(20)
+
+; CHECK: Expand Whens
+
+; CHECK: circuit top :
+; CHECK:   module top :
+; CHECK:     wire p : UInt
+; CHECK:     reg r : UInt
+; CHECK:     p := UInt(1)
+; CHECK:     when p : r := mux(reset, UInt(10), UInt(20))
+
+; CHECK: Finished Expand Whens
+
diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir
new file mode 100644
index 00000000..df6c7034
--- /dev/null
+++ b/test/passes/expand-whens/reg-wdc.fir
@@ -0,0 +1,20 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+circuit top :
+   module top :
+      wire p : UInt
+      p := UInt(1)
+      when p :
+         reg r : UInt
+         r := UInt(20)
+
+; CHECK: Expand Whens
+
+; CHECK: circuit top :
+; CHECK:   module top :
+; CHECK:     wire p : UInt
+; CHECK:     reg r : UInt
+; CHECK:     p := UInt(1)
+; CHECK:     r := UInt(20)
+
+; CHECK: Finished Expand Whens
+
diff --git a/test/passes/expand-whens/reg-wdoc.fir b/test/passes/expand-whens/reg-wdoc.fir
new file mode 100644
index 00000000..ad2089c2
--- /dev/null
+++ b/test/passes/expand-whens/reg-wdoc.fir
@@ -0,0 +1,20 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+circuit top :
+   module top :
+      wire p : UInt
+      when p :
+         reg r : UInt
+         on-reset r := UInt(10)
+         r := UInt(20)
+
+; CHECK: Expand Whens
+
+; CHECK: circuit top :
+; CHECK:   module top :
+; CHECK:     wire p : UInt
+; CHECK:     reg r : UInt
+; CHECK:     p := UInt(1)
+; CHECK:     r := mux(reset, UInt(10), UInt(20))
+
+; CHECK: Finished Expand Whens
+
diff --git a/test/passes/expand-whens/scoped-reg.fir b/test/passes/expand-whens/scoped-reg.fir
index b71a5d50..7f2632f4 100644
--- a/test/passes/expand-whens/scoped-reg.fir
+++ b/test/passes/expand-whens/scoped-reg.fir
@@ -1,5 +1,4 @@
 ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
-; CHECK: Expand Whens
 circuit top :
    module top :
       wire p : UInt
@@ -7,6 +6,13 @@ circuit top :
          reg r : UInt
          on-reset r := UInt(10)
          r := UInt(20)
-; CHECK: r := Register(mux(reset, UInt(10), UInt(20)), mux(reset, UInt(1), p))
-; CHECK: Finished Expand Whens
 
+; CHECK: Expand Whens
+
+; CHECK: circuit top :
+; CHECK:   module top :
+; CHECK:   wire p : UInt
+; CHECK:   reg r : UInt
+; CHECK:   r := mux(reset, UInt(10), UInt(20))
+
+; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/wacc-wdc.fir b/test/passes/expand-whens/wacc-wdc.fir
new file mode 100644
index 00000000..6e407178
--- /dev/null
+++ b/test/passes/expand-whens/wacc-wdc.fir
@@ -0,0 +1,23 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+circuit top :
+   module top :
+      wire p : UInt
+      cmem m : UInt<4>[10]
+      p := UInt(1)
+      when p :
+         write accessor a = m[UInt(3)]
+         a := UInt(20)
+
+; CHECK: Expand Whens
+
+; CHECK: circuit top :
+; CHECK:   module top :
+; CHECK:     wire p : UInt
+; CHECK:     cmem m : UInt<4>[10]
+; CHECK:     write accessor a : m[UInt(3)]
+; CHECK:     p := UInt(1)
+; CHECK:     when p : a := UInt(20)
+
+; CHECK: Finished Expand Whens
+
+