Finished supporting Chisel 2.0 Ref Chip

1 files changed, 12 insertions, 6 deletions

diff --git a/test/chisel3/Test.fir b/test/chisel3/Test.fir
index 1a39b93a..f0d8f80e 100644
--- a/test/chisel3/Test.fir
+++ b/test/chisel3/Test.fir
@@ -3,10 +3,16 @@
 
 circuit Test : 
   module Test : 
-     wire x : UInt
-     x := UInt(0)
-     x := UInt(1)
-     x := UInt(10)
-     x := UInt(21474836)
-     x := UInt("h21474836")
+     input clk : Clock
+     input reset : UInt<1>
+     input falling : UInt<1>
+
+     reg hold : UInt<100>, clk, UInt(1)
+
+     hold := UInt("h42")
+     when reset :
+        hold := UInt("h7f")
+     else :
+        when falling :
+           hold := UInt("h8f")