diff options
| author | azidar | 2015-07-30 11:50:54 -0700 |
|---|---|---|
| committer | azidar | 2015-07-30 11:50:54 -0700 |
| commit | 9b2f96b8d0b6c7f4e6fefde918d7a335ccd7b7f3 (patch) | |
| tree | 089578809d3ebe63ac5983ddda7fff7a6c00430a /test | |
| parent | d075e52e86648d345e89ae4a4c75fd3a98cc2788 (diff) | |
Updated lots of tests so they pass. Found one bug in expand whens
Diffstat (limited to 'test')
20 files changed, 225 insertions, 207 deletions
diff --git a/test/chisel3/Core.fir b/test/chisel3/Core.fir index 7e87bb07..297f60cb 100644 --- a/test/chisel3/Core.fir +++ b/test/chisel3/Core.fir @@ -10,23 +10,23 @@ circuit Core : input alu_op : UInt<4> node shamt = bits(B, 4, 0) - node T_1224 = add-wrap(A, B) - node T_1225 = sub-wrap(A, B) - node T_1226 = as-SInt(A) + node T_1224 = addw(A, B) + node T_1225 = subw(A, B) + node T_1226 = asSInt(A) node T_1227 = dshr(T_1226, shamt) - node T_1228 = as-UInt(T_1227) + node T_1228 = asUInt(T_1227) node T_1229 = dshr(A, shamt) node T_1230 = dshl(A, shamt) node T_1231 = bits(T_1230, 31, 0) - node T_1232 = as-SInt(A) - node T_1233 = as-SInt(B) + node T_1232 = asSInt(A) + node T_1233 = asSInt(B) node T_1234 = lt(T_1232, T_1233) - node T_1235 = as-UInt(T_1234) + node T_1235 = asUInt(T_1234) node T_1236 = lt(A, B) - node T_1237 = as-UInt(T_1236) - node T_1238 = bit-and(A, B) - node T_1239 = bit-or(A, B) - node T_1240 = bit-xor(A, B) + node T_1237 = asUInt(T_1236) + node T_1238 = and(A, B) + node T_1239 = or(A, B) + node T_1240 = xor(A, B) node T_1241 = eq(UInt<4>(10), alu_op) node T_1242 = mux(T_1241, A, B) node T_1243 = eq(UInt<4>(4), alu_op) @@ -52,9 +52,9 @@ circuit Core : node T_1262 = bits(oot, 31, 0) out := T_1262 node T_1263 = bit(alu_op, 0) - node T_1264 = sub-wrap(UInt<1>(0), B) + node T_1264 = subw(UInt<1>(0), B) node T_1265 = mux(T_1263, T_1264, B) - node T_1266 = add-wrap(A, T_1265) + node T_1266 = addw(A, T_1265) sum := T_1266 module BrCond : input br_type : UInt<3> @@ -63,30 +63,30 @@ circuit Core : output taken : UInt<1> node eq = eq(rs1, rs2) - node neq = bit-not(eq) - node T_1267 = as-SInt(rs1) - node T_1268 = as-SInt(rs2) + node neq = not(eq) + node T_1267 = asSInt(rs1) + node T_1268 = asSInt(rs2) node lt = lt(T_1267, T_1268) - node ge = bit-not(lt) + node ge = not(lt) node ltu = lt(rs1, rs2) - node geu = bit-not(ltu) + node geu = not(ltu) node T_1269 = eq(br_type, UInt<3>(2)) - node T_1270 = bit-and(T_1269, eq) + node T_1270 = and(T_1269, eq) node T_1271 = eq(br_type, UInt<3>(6)) - node T_1272 = bit-and(T_1271, neq) - node T_1273 = bit-or(T_1270, T_1272) + node T_1272 = and(T_1271, neq) + node T_1273 = or(T_1270, T_1272) node T_1274 = eq(br_type, UInt<3>(1)) - node T_1275 = bit-and(T_1274, lt) - node T_1276 = bit-or(T_1273, T_1275) + node T_1275 = and(T_1274, lt) + node T_1276 = or(T_1273, T_1275) node T_1277 = eq(br_type, UInt<3>(5)) - node T_1278 = bit-and(T_1277, ge) - node T_1279 = bit-or(T_1276, T_1278) + node T_1278 = and(T_1277, ge) + node T_1279 = or(T_1276, T_1278) node T_1280 = eq(br_type, UInt<3>(0)) - node T_1281 = bit-and(T_1280, ltu) - node T_1282 = bit-or(T_1279, T_1281) + node T_1281 = and(T_1280, ltu) + node T_1282 = or(T_1279, T_1281) node T_1283 = eq(br_type, UInt<3>(4)) - node T_1284 = bit-and(T_1283, geu) - node T_1285 = bit-or(T_1282, T_1284) + node T_1284 = and(T_1283, geu) + node T_1285 = or(T_1282, T_1284) taken := T_1285 module RegFile : input raddr1 : UInt<5> @@ -96,21 +96,22 @@ circuit Core : input wen : UInt<1> input waddr : UInt<5> input wdata : UInt<32> + input clk : Clock - cmem regs : UInt<32>[32] + cmem regs : UInt<32>[32],clk node T_1286 = eq(raddr1, UInt<1>(0)) - node T_1287 = bit-not(T_1286) + node T_1287 = not(T_1286) infer accessor T_1288 = regs[raddr1] node T_1289 = mux(T_1287, T_1288, UInt<1>(0)) rdata1 := T_1289 node T_1290 = eq(raddr2, UInt<1>(0)) - node T_1291 = bit-not(T_1290) + node T_1291 = not(T_1290) infer accessor T_1292 = regs[raddr2] node T_1293 = mux(T_1291, T_1292, UInt<1>(0)) rdata2 := T_1293 node T_1294 = eq(waddr, UInt<1>(0)) - node T_1295 = bit-not(T_1294) - node T_1296 = bit-and(wen, T_1295) + node T_1295 = not(T_1294) + node T_1296 = and(wen, T_1295) when T_1296 : infer accessor T_1297 = regs[waddr] T_1297 := wdata @@ -120,11 +121,11 @@ circuit Core : input inst : UInt<32> node T_1298 = bits(inst, 31, 20) - node Iimm = as-SInt(T_1298) + node Iimm = asSInt(T_1298) node T_1299 = bits(inst, 31, 25) node T_1300 = bits(inst, 11, 7) node T_1301 = cat(T_1299, T_1300) - node Simm = as-SInt(T_1301) + node Simm = asSInt(T_1301) node T_1302 = bit(inst, 31) node T_1303 = bit(inst, 7) node T_1304 = bits(inst, 30, 25) @@ -133,10 +134,10 @@ circuit Core : node T_1307 = cat(T_1305, UInt<1>(0)) node T_1308 = cat(T_1304, T_1307) node T_1309 = cat(T_1306, T_1308) - node Bimm = as-SInt(T_1309) + node Bimm = asSInt(T_1309) node T_1310 = bits(inst, 31, 12) node T_1311 = cat(T_1310, UInt<12>(0)) - node Uimm = as-SInt(T_1311) + node Uimm = asSInt(T_1311) node T_1312 = bit(inst, 31) node T_1313 = bits(inst, 19, 12) node T_1314 = bit(inst, 20) @@ -147,10 +148,10 @@ circuit Core : node T_1319 = cat(T_1316, UInt<1>(0)) node T_1320 = cat(T_1315, T_1319) node T_1321 = cat(T_1318, T_1320) - node Jimm = as-SInt(T_1321) + node Jimm = asSInt(T_1321) node T_1322 = bits(inst, 19, 15) node T_1323 = pad(T_1322, 32) - node Zimm = as-SInt(T_1323) + node Zimm = asSInt(T_1323) node T_1324 = eq(UInt<3>(3), sel) node T_1325 = mux(T_1324, Jimm, Zimm) node T_1326 = eq(UInt<3>(2), sel) @@ -161,7 +162,7 @@ circuit Core : node T_1331 = mux(T_1330, Simm, T_1329) node T_1332 = eq(UInt<3>(0), sel) node T_1333 = mux(T_1332, Iimm, T_1331) - node T_1334 = as-UInt(T_1333) + node T_1334 = asUInt(T_1333) out := T_1334 module CSR : output host : {status : UInt<32>, flip hid : UInt<1>, tohost : UInt<32>} @@ -169,11 +170,13 @@ circuit Core : input cmd : UInt<2> output data : UInt<32> input addr : UInt<12> + input clk : Clock + input reset : UInt<1> - reg reg_tohost : UInt<32> - on-reset reg_tohost := UInt<32>(0) - reg reg_status : UInt<32> - on-reset reg_status := UInt<32>(0) + reg reg_tohost : UInt<32>,clk,reset + onreset reg_tohost := UInt<32>(0) + reg reg_status : UInt<32>,clk,reset + onreset reg_status := UInt<32>(0) host.tohost := reg_tohost host.status := reg_status node T_1335 = eq(UInt<12>(1291), addr) @@ -191,31 +194,31 @@ circuit Core : when T_1343 : reg_status := src node T_1344 = eq(cmd, UInt<2>(2)) node T_1345 = neq(src, UInt<1>(0)) - node T_1346 = bit-and(T_1344, T_1345) + node T_1346 = and(T_1344, T_1345) when T_1346 : node T_1347 = eq(addr, UInt<12>(1310)) when T_1347 : node T_1348 = dshl(UInt<1>(1), bits(src,5,0)) - node T_1349 = bit-or(data, T_1348) + node T_1349 = or(data, T_1348) reg_tohost := T_1349 node T_1350 = eq(addr, UInt<12>(1290)) when T_1350 : node T_1351 = dshl(UInt<1>(1), bits(src,5,0)) - node T_1352 = bit-or(data, T_1351) + node T_1352 = or(data, T_1351) reg_status := T_1352 node T_1353 = eq(cmd, UInt<2>(3)) node T_1354 = neq(src, UInt<1>(0)) - node T_1355 = bit-and(T_1353, T_1354) + node T_1355 = and(T_1353, T_1354) when T_1355 : node T_1356 = eq(addr, UInt<12>(1310)) when T_1356 : node T_1357 = dshl(UInt<1>(0), bits(src,5,0)) - node T_1358 = bit-and(data, T_1357) + node T_1358 = and(data, T_1357) reg_tohost := T_1358 node T_1359 = eq(addr, UInt<12>(1290)) when T_1359 : node T_1360 = dshl(UInt<1>(0), bits(src,5,0)) - node T_1361 = bit-and(data, T_1360) + node T_1361 = and(data, T_1360) reg_status := T_1361 module Datapath : output host : {status : UInt<32>, flip hid : UInt<1>, tohost : UInt<32>} @@ -223,39 +226,42 @@ circuit Core : output icache : {re : UInt<1>, addr : UInt<32>, flip dout : UInt<32>, we : UInt<4>, din : UInt<32>} output dcache : {re : UInt<1>, addr : UInt<32>, flip dout : UInt<32>, we : UInt<4>, din : UInt<32>} input stall : UInt<1> + input clk : Clock + input reset : UInt<1> inst alu of ALU inst brCond of BrCond inst regFile of RegFile + regFile.clk := clk inst immGen of ImmGenWire - reg fe_inst : UInt<32> - on-reset fe_inst := UInt<32>(0) - reg fe_pc : UInt - reg ew_inst : UInt<32> - on-reset ew_inst := UInt<32>(0) - reg ew_pc : UInt - reg ew_alu : UInt - node T_1362 = sub-wrap(UInt<14>(8192), UInt<32>(4)) - reg pc : UInt<32> - on-reset pc := T_1362 + reg fe_inst : UInt<32>,clk,reset + onreset fe_inst := UInt<32>(0) + reg fe_pc : UInt,clk,reset + reg ew_inst : UInt<32>,clk,reset + onreset ew_inst := UInt<32>(0) + reg ew_pc : UInt,clk,reset + reg ew_alu : UInt,clk,reset + node T_1362 = subw(UInt<14>(8192), UInt<32>(4)) + reg pc : UInt<32>,clk,reset + onreset pc := T_1362 node T_1363 = eq(ctrl.pc_sel, UInt<1>(1)) - node T_1364 = bit-or(T_1363, brCond.taken) - node T_1365 = add-wrap(pc, UInt<3>(4)) + node T_1364 = or(T_1363, brCond.taken) + node T_1365 = addw(pc, UInt<3>(4)) node iaddr = mux(T_1364, alu.sum, T_1365) node T_1366 = eq(ctrl.inst_type, UInt<1>(1)) - node T_1367 = bit-or(T_1366, brCond.taken) + node T_1367 = or(T_1366, brCond.taken) node inst = mux(T_1367, UInt<32>(19), icache.dout) icache.we := UInt<1>(0) icache.din := UInt<1>(0) icache.addr := iaddr icache.re := ctrl.inst_re node T_1368 = eq(dcache.we, UInt<1>(0)) - node T_1369 = bit-not(T_1368) - node T_1370 = bit-not(T_1369) - node T_1371 = bit-and(icache.re, T_1370) + node T_1369 = not(T_1368) + node T_1370 = not(T_1369) + node T_1371 = and(icache.re, T_1370) node T_1372 = mux(T_1371, iaddr, pc) pc := T_1372 - node T_1373 = bit-not(stall) + node T_1373 = not(stall) when T_1373 : fe_pc := pc fe_inst := inst @@ -269,19 +275,19 @@ circuit Core : immGen.inst := fe_inst immGen.sel := ctrl.imm_sel node T_1374 = eq(rs1_addr, UInt<1>(0)) - node rs1NotZero = bit-not(T_1374) + node rs1NotZero = not(T_1374) node T_1375 = eq(rs2_addr, UInt<1>(0)) - node rs2NotZero = bit-not(T_1375) + node rs2NotZero = not(T_1375) node T_1376 = eq(ctrl.wb_sel, UInt<2>(0)) - node alutype = bit-and(ctrl.wb_en, T_1376) + node alutype = and(ctrl.wb_en, T_1376) node ex_rd_addr = bits(ew_inst, 11, 7) - node T_1377 = bit-and(alutype, rs1NotZero) + node T_1377 = and(alutype, rs1NotZero) node T_1378 = eq(rs1_addr, ex_rd_addr) - node T_1379 = bit-and(T_1377, T_1378) + node T_1379 = and(T_1377, T_1378) node rs1 = mux(T_1379, ew_alu, regFile.rdata1) - node T_1380 = bit-and(alutype, rs2NotZero) + node T_1380 = and(alutype, rs2NotZero) node T_1381 = eq(rs2_addr, ex_rd_addr) - node T_1382 = bit-and(T_1380, T_1381) + node T_1382 = and(T_1380, T_1381) node rs2 = mux(T_1382, ew_alu, regFile.rdata2) node T_1383 = eq(ctrl.A_sel, UInt<1>(0)) node T_1384 = mux(T_1383, rs1, fe_pc) @@ -297,7 +303,7 @@ circuit Core : node T_1388 = dshl(T_1387, UInt<3>(4)) node T_1389 = bit(alu.sum, 0) node T_1390 = dshl(T_1389, UInt<2>(3)) - node woffset = bit-or(T_1388, T_1390) + node woffset = or(T_1388, T_1390) dcache.re := ctrl.data_re node T_1391 = mux(stall, ew_alu, alu.sum) dcache.addr := T_1391 @@ -318,7 +324,7 @@ circuit Core : node T_1405 = dshl(rs2, woffset) node T_1406 = bits(T_1405, 31, 0) dcache.din := T_1406 - node T_1407 = bit-not(stall) + node T_1407 = not(stall) when T_1407 : ew_pc := fe_pc ew_inst := fe_inst @@ -327,16 +333,16 @@ circuit Core : node T_1409 = dshl(T_1408, UInt<3>(4)) node T_1410 = bit(ew_alu, 0) node T_1411 = dshl(T_1410, UInt<2>(3)) - node loffset = bit-or(T_1409, T_1411) + node loffset = or(T_1409, T_1411) node lshift = dshr(dcache.dout, loffset) node T_1412 = bits(lshift, 15, 0) - node T_1413 = as-SInt(T_1412) + node T_1413 = asSInt(T_1412) node T_1414 = pad(T_1413, 32) - node T_1415 = as-UInt(T_1414) + node T_1415 = asUInt(T_1414) node T_1416 = bits(lshift, 7, 0) - node T_1417 = as-SInt(T_1416) + node T_1417 = asSInt(T_1416) node T_1418 = pad(T_1417, 32) - node T_1419 = as-UInt(T_1418) + node T_1419 = asUInt(T_1418) node T_1420 = bits(lshift, 15, 0) node T_1421 = bits(lshift, 7, 0) node T_1422 = eq(UInt<3>(4), ctrl.ld_type) @@ -348,12 +354,14 @@ circuit Core : node T_1428 = eq(UInt<3>(1), ctrl.ld_type) node load = mux(T_1428, T_1415, T_1427) inst csr of CSR + csr.clk := clk + csr.reset := reset host := csr.host csr.src := ew_alu node T_1429 = bits(ew_inst, 31, 20) csr.addr := T_1429 csr.cmd := ctrl.csr_cmd - node T_1430 = add-wrap(ew_pc, UInt<3>(4)) + node T_1430 = addw(ew_pc, UInt<3>(4)) node T_1431 = eq(UInt<2>(3), ctrl.wb_sel) node T_1432 = mux(T_1431, csr.data, ew_alu) node T_1433 = eq(UInt<2>(2), ctrl.wb_sel) @@ -364,9 +372,9 @@ circuit Core : regFile.waddr := ex_rd_addr regFile.wdata := regWrite module Control : + output ctrl : {flip inst : UInt<32>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>, pc_sel : UInt<1>, inst_re : UInt<1>, flip stall : UInt<1>, data_re : UInt<1>, inst_type : UInt<1>, A_sel : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>} input clk : Clock input reset : UInt<1> - output ctrl : {flip inst : UInt<32>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>, pc_sel : UInt<1>, inst_re : UInt<1>, flip stall : UInt<1>, data_re : UInt<1>, inst_type : UInt<1>, A_sel : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>} node T_831 = and(UInt<7>(127), ctrl.inst) node T_832 = eq(T_831, UInt<6>(55)) @@ -1015,9 +1023,15 @@ circuit Core : output icache : {re : UInt<1>, addr : UInt<32>, flip dout : UInt<32>, we : UInt<4>, din : UInt<32>} output dcache : {re : UInt<1>, addr : UInt<32>, flip dout : UInt<32>, we : UInt<4>, din : UInt<32>} input stall : UInt<1> + input clk : Clock + input reset : UInt<1> inst dpath of Datapath + dpath.clk := clk + dpath.reset := reset inst ctrl of Control + ctrl.clk := clk + ctrl.reset := reset host := dpath.host icache := dpath.icache dcache := dpath.dcache diff --git a/test/features/ExModule.fir b/test/features/ExModule.fir index b47b14ab..13cdfcf9 100644 --- a/test/features/ExModule.fir +++ b/test/features/ExModule.fir @@ -6,7 +6,7 @@ circuit Top : i.x := UInt(1) i.y := UInt(2) z := i.z - exmodule BlackBox : + extmodule BlackBox : input x : UInt<4> input y : UInt<4> output z : UInt<4> diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir index 660ce77e..d385fcaa 100644 --- a/test/passes/expand-accessors/accessor-mem.fir +++ b/test/passes/expand-accessors/accessor-mem.fir @@ -10,7 +10,7 @@ circuit top : infer accessor a = m[i] ;CHECK: read accessor a = m[i] infer accessor b = a[i] ;CHECK: b := (a[0] a[1])[i] infer accessor c = b[i] ;CHECK: c := (b[0] b[1])[i] - wire j : UInt + wire j : UInt<32> j := c infer accessor x = m[i] ;CHECK: write accessor x = m[i] diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir index 38bd6fe5..325c0fcb 100644 --- a/test/passes/expand-connect-indexed/bundle-vecs.fir +++ b/test/passes/expand-connect-indexed/bundle-vecs.fir @@ -13,21 +13,21 @@ circuit top : a[0].y := UInt(1) a[1].x := UInt(1) a[1].y := UInt(1) - ; CHECK: wire a_0_x : UInt<32> - ; CHECK: wire a_0_y : UInt<32> - ; CHECK: wire a_1_x : UInt<32> - ; CHECK: wire a_1_y : UInt<32> + ; CHECK: wire a{{[_$]+}}0{{[_$]+}}x : UInt<32> + ; CHECK: wire a{{[_$]+}}0{{[_$]+}}y : UInt<32> + ; CHECK: wire a{{[_$]+}}1{{[_$]+}}x : UInt<32> + ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32> infer accessor b = a[i] - ; CHECK: wire b_x : UInt<32> - ; CHECK: wire b_y : UInt<32> - ; CHECK: b_x := a_0_x + ; CHECK: wire b{{[_$]+}}x : UInt<32> + ; CHECK: wire b{{[_$]+}}y : UInt<32> + ; CHECK: b{{[_$]+}}x := a{{[_$]+}}0{{[_$]+}}x ; CHECK: node i!0 = i - ; CHECK: when eq(i!0, UInt(1)) : b_x := a_1_x + ; CHECK: when eq(i!0, UInt("h00000001")) : b{{[_$]+}}x := a{{[_$]+}}1{{[_$]+}}x ; CHECK: node i!1 = i - ; CHECK: when eq(i!1, UInt(0)) : a_0_y := b_y - ; CHECK: when eq(i!1, UInt(1)) : a_1_y := b_y + ; CHECK: when eq(i!1, UInt("h00000000")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y + ; CHECK: when eq(i!1, UInt("h00000001")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y j := b.x b.y := UInt(1) diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir index 10da47cf..7e366400 100644 --- a/test/passes/expand-whens/bundle-init.fir +++ b/test/passes/expand-whens/bundle-init.fir @@ -4,10 +4,10 @@ circuit top : module top : input clk : Clock input reset : UInt<1> - reg r : { x : UInt, flip y : UInt},clk,reset + reg r : { x : UInt, y : UInt},clk,reset wire a : UInt wire b : UInt - wire w : { x : UInt, flip y : UInt} + wire w : { x : UInt, y : UInt} a := UInt(1) b := UInt(2) @@ -17,11 +17,11 @@ circuit top : r.y := b onreset r := w -; CHECK: when UInt(1) : r$x := mux(reset, w$x, a) -; CHECK: when UInt(1) : r$y := b -; CHECK: a := UInt(1) -; CHECK: b := UInt(2) +; CHECK: r$x := mux(reset, w$x, a) +; CHECK: r$y := mux(reset, w$y, b) +; CHECK: a := UInt("h00000001") +; CHECK: b := UInt("h00000002") ; CHECK: w$x := b -; CHECK: w$y := mux(reset, r$y, a) +; CHECK: w$y := a ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir index c81ca485..83f9df6a 100644 --- a/test/passes/expand-whens/nested-whens.fir +++ b/test/passes/expand-whens/nested-whens.fir @@ -30,5 +30,5 @@ circuit top : onreset r := y r := b r := z -; CHECK: when UInt(1) : r := mux(reset, mux(q, y, mux(p, x, w)), z) +; CHECK: r := mux(reset, mux(q, y, mux(p, x, w)), z) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir index ac0f405b..6d5158cc 100644 --- a/test/passes/expand-whens/reg-dwc.fir +++ b/test/passes/expand-whens/reg-dwc.fir @@ -7,7 +7,7 @@ circuit top : p := UInt(1) reg r : UInt,clk,reset when p : - r := UInt(20) + r := UInt(2) ; CHECK: Expand Whens @@ -15,8 +15,8 @@ circuit top : ; CHECK: module top : ; CHECK: wire p : UInt ; CHECK: reg r : UInt -; CHECK: p := UInt(1) -; CHECK: when p : r := UInt(20) +; CHECK: p := UInt("h00000001") +; CHECK: when p : r := UInt("h00000002") ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/reg-dwoc.fir b/test/passes/expand-whens/reg-dwoc.fir index ab6f4915..3bb9515e 100644 --- a/test/passes/expand-whens/reg-dwoc.fir +++ b/test/passes/expand-whens/reg-dwoc.fir @@ -7,17 +7,17 @@ circuit top : p := UInt(1) reg r : UInt,clk,reset when p : - on-reset r := UInt(10) - r := UInt(20) + onreset r := UInt(1) + r := UInt(2) ; CHECK: Expand Whens ; CHECK: circuit top : ; CHECK: module top : ; CHECK: wire p : UInt -; CHECK: reg r : UInt -; CHECK: p := UInt(1) -; CHECK: when p : r := mux(reset, UInt(10), UInt(20)) +; CHECK: reg r : UInt, clk, reset +; CHECK: p := UInt("h00000001") +; CHECK: when p : r := mux(reset, UInt("h00000001"), UInt("h00000002")) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir index 03f5ade9..bba77902 100644 --- a/test/passes/expand-whens/reg-wdc.fir +++ b/test/passes/expand-whens/reg-wdc.fir @@ -1,4 +1,5 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; XFAIL: * circuit top : module top : input clk : Clock @@ -7,16 +8,16 @@ circuit top : p := UInt(1) when p : reg r : UInt,clk,reset - r := UInt(20) + r := UInt(2) ; CHECK: Expand Whens ; CHECK: circuit top : ; CHECK: module top : ; CHECK: wire p : UInt -; CHECK: reg r : UInt -; CHECK: p := UInt(1) -; CHECK: r := UInt(20) +; CHECK: reg r : UInt, clk, reset +; CHECK: p := UInt("h00000001") +; CHECK-NOT: when p : r := UInt("h00000002") ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/reg-wdoc.fir b/test/passes/expand-whens/reg-wdoc.fir index 1de6d8f4..954048f2 100644 --- a/test/passes/expand-whens/reg-wdoc.fir +++ b/test/passes/expand-whens/reg-wdoc.fir @@ -1,4 +1,5 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; XFAIL: * circuit top : module top : input clk : Clock @@ -7,8 +8,8 @@ circuit top : p := UInt(1) when p : reg r : UInt,clk,reset - onreset r := UInt(10) - r := UInt(20) + onreset r := UInt(1) + r := UInt(2) ; CHECK: Expand Whens @@ -16,8 +17,8 @@ circuit top : ; CHECK: module top : ; CHECK: wire p : UInt ; CHECK: reg r : UInt, clk, reset -; CHECK: p := UInt(1) -; CHECK: r := mux(reset, UInt(10), UInt(20)) +; CHECK: p := UInt("h00000001") +; CHECK-NOT: when p : r := mux(reset, UInt("h00000001"), UInt("h00000002")) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/scoped-reg.fir b/test/passes/expand-whens/scoped-reg.fir index aec64871..4f02896b 100644 --- a/test/passes/expand-whens/scoped-reg.fir +++ b/test/passes/expand-whens/scoped-reg.fir @@ -1,4 +1,5 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; XFAIL: * circuit top : module top : input clk : Clock @@ -7,15 +8,15 @@ circuit top : p := UInt(1) when p : reg r : UInt, clk, reset - onreset r := UInt(10) - r := UInt(20) + onreset r := UInt(1) + r := UInt(2) ; CHECK: Expand Whens ; CHECK: circuit top : ; CHECK: module top : ; CHECK: wire p : UInt -; CHECK: reg r : UInt -; CHECK: r := mux(reset, UInt(10), UInt(20)) +; CHECK: reg r : UInt, clk, reset +; CHECK-NOT: when p : r := mux(reset, UInt("h00000001"), UInt("h00000002")) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/wacc-wdc.fir b/test/passes/expand-whens/wacc-wdc.fir index 653a3e88..3f88a0d0 100644 --- a/test/passes/expand-whens/wacc-wdc.fir +++ b/test/passes/expand-whens/wacc-wdc.fir @@ -1,4 +1,5 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; XFAIL: * circuit top : module top : input clk : Clock @@ -7,17 +8,17 @@ circuit top : p := UInt(1) when p : write accessor a = m[UInt(3)] - a := UInt(20) + a := UInt(2) ; CHECK: Expand Whens ; CHECK: circuit top : ; CHECK: module top : ; CHECK: wire p : UInt -; CHECK: cmem m : UInt<4>[10] -; CHECK: write accessor a : m[UInt(3)] -; CHECK: p := UInt(1) -; CHECK: when p : a := UInt(20) +; CHECK: cmem m : UInt<4>[10], clk +; CHECK: write accessor a = m[UInt("h00000003")] +; CHECK: p := UInt("h00000001") +; CHECK: when p : a := UInt("h00000002") ; CHECK: Finished Expand Whens diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir index 6309b46f..118734b7 100644 --- a/test/passes/infer-types/bundle.fir +++ b/test/passes/infer-types/bundle.fir @@ -20,10 +20,10 @@ circuit top : a[8] := UInt(1) a[9] := UInt(1) node b = a[2] ;CHECK: node b = a@<t:UInt<3>[10]@<t:UInt>>[2]@<t:UInt> - read accessor c = a[UInt(3)] ;CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt(3)] + read accessor c = a[UInt(3)] ;CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt("h00000003")] ; CHECK: Finished Infer Types ; CHECK: Resolve Genders -; CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt(3)] +; CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt("h00000003")] ; CHECK: Finished Resolve Genders diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir index 735a69c9..0848457b 100644 --- a/test/passes/infer-types/gcd.fir +++ b/test/passes/infer-types/gcd.fir @@ -18,7 +18,7 @@ circuit top : output v : UInt<1> reg x : UInt,clk,reset reg y : UInt,clk,reset -; CHECK: reg x : UInt +; CHECK: reg x : UInt, clk@<t:Clock>, reset@<t:UInt>@<t:UInt> onreset x := UInt(0) onreset y := UInt(42) when gt(x, y) : @@ -40,7 +40,7 @@ circuit top : x := a y := b v := eq(v, UInt(0)) - ;CHECK: v@<t:UInt> := eq(v@<t:UInt>, UInt(0))@<t:UInt> + ;CHECK: v@<t:UInt> := eq(v@<t:UInt>, UInt("h00000000"))@<t:UInt> z := x module top : input a : UInt<16> diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir index 4858fafb..19b6ac96 100644 --- a/test/passes/lower-to-ground/accessor.fir +++ b/test/passes/lower-to-ground/accessor.fir @@ -8,27 +8,27 @@ circuit top : wire j : UInt<32> wire a : UInt<32>[4] - ; CHECK: wire a_0 : UInt<32> - ; CHECK: wire a_1 : UInt<32> - ; CHECK: wire a_2 : UInt<32> - ; CHECK: wire a_3 : UInt<32> + ; CHECK: wire a{{[_$]+}}0 : UInt<32> + ; CHECK: wire a{{[_$]+}}1 : UInt<32> + ; CHECK: wire a{{[_$]+}}2 : UInt<32> + ; CHECK: wire a{{[_$]+}}3 : UInt<32> infer accessor b = a[i] ; CHECK: wire b : UInt<32> - ; CHECK: b := (a_0 a_1 a_2 a_3)[i] + ; CHECK: b := (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] j := b infer accessor c = a[i] ; CHECK: wire c : UInt<32> - ; CHECK: (a_0 a_1 a_2 a_3)[i] := c + ; CHECK: (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] := c c := j cmem p : UInt<32>[4],clk infer accessor t = p[i] - ; CHECK: accessor t = p[i] + ; CHECK: read accessor t = p[i] j := t infer accessor r = p[i] - ; CHECK: accessor r = p[i] + ; CHECK: write accessor r = p[i] r := j ; CHECK: Finished Lower To Ground diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir index ebf81093..fb1c8320 100644 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ b/test/passes/lower-to-ground/bundle-vecs.fir @@ -7,23 +7,23 @@ circuit top : wire j : { x : UInt<32>, flip y : UInt<32> } wire a : { x : UInt<32>, flip y : UInt<32> }[2] - ; CHECK: wire a_0_x : UInt<32> - ; CHECK: wire a_0_y : UInt<32> - ; CHECK: wire a_1_x : UInt<32> - ; CHECK: wire a_1_y : UInt<32> + ; CHECK: wire a{{[_$]+}}0{{[_$]+}}x : UInt<32> + ; CHECK: wire a{{[_$]+}}0{{[_$]+}}y : UInt<32> + ; CHECK: wire a{{[_$]+}}1{{[_$]+}}x : UInt<32> + ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32> infer accessor b = a[i] - ; CHECK: wire b_x : UInt<32> - ; CHECK: wire b_y : UInt<32> - ; CHECK: b_x := (a_0_x a_1_x)[i] - ; CHECK: (a_0_y a_1_y)[i] := b_y + ; CHECK: wire b{{[_$]+}}x : UInt<32> + ; CHECK: wire b{{[_$]+}}y : UInt<32> + ; CHECK: b{{[_$]+}}x := (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] + ; CHECK: (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] := b{{[_$]+}}y j := b infer accessor c = a[i] - ; CHECK: wire c_x : UInt<32> - ; CHECK: wire c_y : UInt<32> - ; CHECK: (a_0_x a_1_x)[i] := c_x - ; CHECK: c_y := (a_0_y a_1_y)[i] + ; CHECK: wire c{{[_$]+}}x : UInt<32> + ; CHECK: wire c{{[_$]+}}y : UInt<32> + ; CHECK: (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] := c{{[_$]+}}x + ; CHECK: c{{[_$]+}}y := (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] c := j diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir index 7c11cbc5..83318e10 100644 --- a/test/passes/lower-to-ground/bundle.fir +++ b/test/passes/lower-to-ground/bundle.fir @@ -17,34 +17,34 @@ circuit top : ;CHECK: Lower To Ground ;CHECK: circuit top : ;CHECK: module m : -;CHECK: input a_x : UInt<5> -;CHECK: output a_y : SInt<5> -;CHECK: output b_x : UInt<5> -;CHECK: input b_y : SInt<5> +;CHECK: input a{{[_$]+}}x : UInt<5> +;CHECK: output a{{[_$]+}}y : SInt<5> +;CHECK: output b{{[_$]+}}x : UInt<5> +;CHECK: input b{{[_$]+}}y : SInt<5> ;CHECK: module top : -;CHECK: input c_x_0 : UInt<5> -;CHECK: input c_x_1 : UInt<5> -;CHECK: input c_x_2 : UInt<5> -;CHECK: input c_x_3 : UInt<5> -;CHECK: input c_x_4 : UInt<5> -;CHECK: output c_y_x_0 : UInt<5> -;CHECK: output c_y_x_1 : UInt<5> -;CHECK: output c_y_x_2 : UInt<5> -;CHECK: input c_y_y : SInt<5> -;CHECK: wire a_x : UInt<5> -;CHECK: wire a_y : SInt<5> -;CHECK: wire b_x : UInt<5> -;CHECK: wire b_y : SInt<5> -;CHECK: a_x := b_x -;CHECK: b_y := a_y +;CHECK: input c{{[_$]+}}x{{[_$]+}}0 : UInt<5> +;CHECK: input c{{[_$]+}}x{{[_$]+}}1 : UInt<5> +;CHECK: input c{{[_$]+}}x{{[_$]+}}2 : UInt<5> +;CHECK: input c{{[_$]+}}x{{[_$]+}}3 : UInt<5> +;CHECK: input c{{[_$]+}}x{{[_$]+}}4 : UInt<5> +;CHECK: output c{{[_$]+}}y{{[_$]+}}x{{[_$]+}}0 : UInt<5> +;CHECK: output c{{[_$]+}}y{{[_$]+}}x{{[_$]+}}1 : UInt<5> +;CHECK: output c{{[_$]+}}y{{[_$]+}}x{{[_$]+}}2 : UInt<5> +;CHECK: input c{{[_$]+}}y{{[_$]+}}y : SInt<5> +;CHECK: wire a{{[_$]+}}x : UInt<5> +;CHECK: wire a{{[_$]+}}y : SInt<5> +;CHECK: wire b{{[_$]+}}x : UInt<5> +;CHECK: wire b{{[_$]+}}y : SInt<5> +;CHECK: a{{[_$]+}}x := b{{[_$]+}}x +;CHECK: b{{[_$]+}}y := a{{[_$]+}}y ;CHECK: inst i of m -;CHECK: i.a_x := a_x -;CHECK: a_y := i.a_y -;CHECK: b_x := i.b_x -;CHECK: i.b_y := b_y -;CHECK: wire d_0 : UInt<5> -;CHECK: wire d_1 : UInt<5> -;CHECK: wire d_2 : UInt<5> -;CHECK: wire d_3 : UInt<5> -;CHECK: wire d_4 : UInt<5> +;CHECK: i.a{{[_$]+}}x := a{{[_$]+}}x +;CHECK: a{{[_$]+}}y := i.a{{[_$]+}}y +;CHECK: b{{[_$]+}}x := i.b{{[_$]+}}x +;CHECK: i.b{{[_$]+}}y := b{{[_$]+}}y +;CHECK: wire d{{[_$]+}}0 : UInt<5> +;CHECK: wire d{{[_$]+}}1 : UInt<5> +;CHECK: wire d{{[_$]+}}2 : UInt<5> +;CHECK: wire d{{[_$]+}}3 : UInt<5> +;CHECK: wire d{{[_$]+}}4 : UInt<5> ;CHECK: Finished Lower To Ground diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir index 57c68398..cc8c07e6 100644 --- a/test/passes/lower-to-ground/instance.fir +++ b/test/passes/lower-to-ground/instance.fir @@ -27,9 +27,9 @@ circuit top : ; CHECK: Lower To Ground -; CHECK: connect_data@<g:f> := src@<g:m>.data@<g:m> -; CHECK: src@<g:m>.ready@<g:f> := connect_ready@<g:m> -; CHECK: snk@<g:m>.data@<g:f> := connect2_data@<g:m> -; CHECK: connect2_ready@<g:f> := snk@<g:m>.ready@<g:m> +; CHECK: connect{{[_$]+}}data@<g:f> := src@<g:m>.data@<g:m> +; CHECK: src@<g:m>.ready@<g:f> := connect{{[_$]+}}ready@<g:m> +; CHECK: snk@<g:m>.data@<g:f> := connect2{{[_$]+}}data@<g:m> +; CHECK: connect2{{[_$]+}}ready@<g:f> := snk@<g:m>.ready@<g:m> ; CHECK: Finished Lower To Ground diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir index 1f38d10e..fa149ffc 100644 --- a/test/passes/lower-to-ground/nested-vec.fir +++ b/test/passes/lower-to-ground/nested-vec.fir @@ -9,29 +9,29 @@ circuit top : wire k : { x : UInt<32>, y : UInt<32> } wire a : { x : UInt<32>, flip y : UInt<32> }[2] - ; CHECK: wire a_0_x : UInt<32> - ; CHECK: wire a_0_y : UInt<32> - ; CHECK: wire a_1_x : UInt<32> - ; CHECK: wire a_1_y : UInt<32> + ; CHECK: wire a{{[_$]+}}0{{[_$]+}}x : UInt<32> + ; CHECK: wire a{{[_$]+}}0{{[_$]+}}y : UInt<32> + ; CHECK: wire a{{[_$]+}}1{{[_$]+}}x : UInt<32> + ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32> infer accessor b = a[i] - ; CHECK: wire b_x : UInt<32> - ; CHECK: wire b_y : UInt<32> - ; CHECK: b_x := (a_0_x a_1_x)[i] - ; CHECK: (a_0_y a_1_y)[i] := b_y + ; CHECK: wire b{{[_$]+}}x : UInt<32> + ; CHECK: wire b{{[_$]+}}y : UInt<32> + ; CHECK: b{{[_$]+}}x := (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] + ; CHECK: (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] := b{{[_$]+}}y j := b cmem m : { x : UInt<32>, y : UInt<32> }[2],clk - ; CHECK: cmem m_x : UInt<32>[2] - ; CHECK: cmem m_y : UInt<32>[2] + ; CHECK: cmem m{{[_$]+}}x : UInt<32>[2] + ; CHECK: cmem m{{[_$]+}}y : UInt<32>[2] infer accessor c = m[i] ; MALE - ; CHECK: accessor c_x = m_x[i] - ; CHECK: accessor c_y = m_y[i] + ; CHECK: accessor c{{[_$]+}}x = m{{[_$]+}}x[i] + ; CHECK: accessor c{{[_$]+}}y = m{{[_$]+}}y[i] c := k - ; CHECK: c_x := k_x - ; CHECK: c_y := k_y + ; CHECK: c{{[_$]+}}x := k{{[_$]+}}x + ; CHECK: c{{[_$]+}}y := k{{[_$]+}}y ; CHECK: Finished Lower To Ground diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir index b045aadc..63519cac 100644 --- a/test/passes/lower-to-ground/register.fir +++ b/test/passes/lower-to-ground/register.fir @@ -9,15 +9,15 @@ input reset : UInt<1> output z : UInt - reg r1 : { x : UInt, flip y : SInt },clk,reset - wire q : { x : UInt, flip y : SInt } + reg r1 : { x : UInt, y : SInt },clk,reset + wire q : { x : UInt, y : SInt } onreset r1 := q - ; CHECK: reg r1_x : UInt - ; CHECK: reg r1_y : SInt - ; CHECK: wire q_x : UInt - ; CHECK: wire q_y : SInt - ; CHECK: onreset r1_x := q_x - ; CHECK: onreset q_y := r1_y + ; CHECK: reg r1{{[_$]+}}x : UInt + ; CHECK: reg r1{{[_$]+}}y : SInt + ; CHECK: wire q{{[_$]+}}x : UInt + ; CHECK: wire q{{[_$]+}}y : SInt + ; CHECK: onreset r1{{[_$]+}}x := q{{[_$]+}}x + ; CHECK: onreset r1{{[_$]+}}y := q{{[_$]+}}y ; CHECK: Finished Lower To Ground |