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| author | Adam Izraelevitz | 2015-07-28 13:29:55 -0700 |
|---|---|---|
| committer | Adam Izraelevitz | 2015-07-28 13:29:55 -0700 |
| commit | 0c7aca561aef907314b0d9c9737fcea04ae6ce82 (patch) | |
| tree | 1b5a4da96413bd34d6b5e05ed2cbb2312d1a4b1d /test | |
| parent | 69e4bc2c4f4e7c2940633f12a40a5550205eb75e (diff) | |
Integrated bigint. Mostly works, but getting "cast" error for make Test.
Diffstat (limited to 'test')
| -rw-r--r-- | test/chisel3/Test.fir | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/test/chisel3/Test.fir b/test/chisel3/Test.fir new file mode 100644 index 00000000..aea7acde --- /dev/null +++ b/test/chisel3/Test.fir @@ -0,0 +1,9 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s +; CHECK: Done! + +circuit Test : + module Test : + wire x : UInt<10> + x := UInt(5151) + x := UInt(515151512512412414124124124124) + |