| Age | Commit message (Expand) | Author |
|---|
| 2016-01-29 | Fix no space after "flip" for flipped fields in Scala FIRRTL, also make Scala... | Jack |
| 2016-01-29 | Changed reg syntax to new "with" semantics in Scala FIRRTL | Jack |
| 2016-01-28 | Add support for single-line and multi-line scoping to Scala FIRRTL preprocess... | Jack |
| 2016-01-28 | Fixed bug on translating SubAccess concrete syntax to abstract in Scala FIRRTL | Jack |
| 2016-01-28 | WIP Added support for mux to Scala FIRRTL | jackkoenig |
| 2016-01-28 | WIP Added support for is invalid and validif to Scala FIRRTL | jackkoenig |
| 2016-01-28 | WIP Added support for stop to Scala FIRRTL | jackkoenig |
| 2016-01-28 | WIP Added support for printf to Scala FIRRTL | jackkoenig |
| 2016-01-28 | WIP: Added support for FIRRTL 0.2.0 Memories to Scala FIRRTL | jackkoenig |
| 2016-01-28 | Move IntLit ANTLR lexer rule to before String lexer rule to ensure IntLit of ... | jackkoenig |
| 2016-01-28 | Merge branch 'new-reg-prims' of github.com:ucb-bar/firrtl | azidar |
| 2016-01-28 | Fixed bug where subaccess indexes were being classified as female, | azidar |
| 2016-01-28 | Changed rmode to wmode | azidar |
| 2016-01-28 | Use IsInvalid instead of Poisons in chirrtl -> firrtl transform | azidar |
| 2016-01-28 | Fixed bug where you cannot extract from a single bit wire in verilog. #55. | azidar |
| 2016-01-28 | Fixed bug where needed to cast bit-operation inputs prior to verilog emission | azidar |
| 2016-01-28 | Added addw to working ir as an optimized verilog emission | azidar |
| 2016-01-28 | Add map of symbol->symbol for wdefinstance | azidar |
| 2016-01-28 | Fixed matching on types for and, or, and xor | azidar |
| 2016-01-28 | Fixed bug and updated test for changing mod to rem | azidar |
| 2016-01-28 | Changed mod to rem | azidar |
| 2016-01-28 | Updated with new primops. Removed addw,subw,quo,rem,bit. Added head,tail,asCl... | azidar |
| 2016-01-28 | Fixed readwriter syntax, and all printed mstats to use => instead of a colon | azidar |
| 2016-01-28 | Changed register syntax for optional reset and init values | azidar |
| 2016-01-27 | WIP Moving Scala FIRRTL to match spec 0.2.0. Not everything is implemented (n... | jackkoenig |
| 2016-01-27 | Reworked readwriter types | azidar |
| 2016-01-27 | Fixed additional tests and inferring rdwr ports in chirrtl | jackkoenig |
| 2016-01-27 | Merge branch 'scala-new-mem' | jackkoenig |
| 2016-01-25 | Fixed bug where poisons were not being declared | azidar |
| 2016-01-25 | Added verilog rename pass | azidar |
| 2016-01-25 | Added isinvalid and validif | azidar |
| 2016-01-25 | Removed println in expand when | azidar |
| 2016-01-25 | Fixed width inference bug for muxes | azidar |
| 2016-01-25 | Removed random println | azidar |
| 2016-01-25 | Fixed support for muxes and nodes with passive aggregate types | azidar |
| 2016-01-25 | Changed first generated name to use _0 postfix | azidar |
| 2016-01-24 | Made CInfer robust to high firrtl errors | azidar |
| 2016-01-24 | Added muxing on passive aggregate types | azidar |
| 2016-01-24 | Merge branch 'new-mem' of github.com:ucb-bar/firrtl into new-mem | azidar |
| 2016-01-24 | Removed hashing as it made refchip slower to compile | azidar |
| 2016-01-24 | Added DefMemory to CInfer Types | azidar |
| 2016-01-23 | Fix Verilog syntax errors for print/stop | Andrew Waterman |
| 2016-01-23 | Removed buggy optimization of dshr and dshl | azidar |
| 2016-01-23 | Moved inst declarations after other declarations | azidar |
| 2016-01-23 | Fixed commas for instances in verilog | azidar |
| 2016-01-23 | Added more semicolons | azidar |
| 2016-01-23 | Added semicolon after assigns in verilog | azidar |
| 2016-01-23 | off by one error when emitting ports in verilog | azidar |
| 2016-01-23 | Fixed combinational read verilog backend | azidar |
| 2016-01-23 | Removed more prints ;) | azidar |
