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2015-08-17Removed leading zeros from UInt constantsazidar
2015-08-17Fixed bug where equality between expressions was incorrect, leading toazidar
an optimization that eliminated some when statements. Added test case.
2015-08-17Added tests for shl and mem. Fixed bug in verilog output of mem size.azidar
2015-08-04Added check for reading from outputs with flipsazidar
2015-08-04Added verilog keywords to uniquify themazidar
2015-08-04Fixed reading from instance's input ports. Fixed unique naming bug.azidar
2015-08-03Changed name mangling to use _ as a delin. Fixed bug in checking forazidar
invalid <> assignments.
2015-08-03Fixed performance bug in Split Expressions. Changed delin for connect ↵azidar
indexed. Fixed various broken tests.
2015-07-31Reading from output ports no longer causes errorsazidar
2015-07-31Added errors for bulk connects where field names match but types/flips don'tazidar
2015-07-31Updated tests to pipe from stderr to stdoutazidar
2015-07-30Added module name to error messages.azidar
2015-07-30Updated error and feature tests. Fixed bug in detecting incorrect gendersazidar
2015-07-30Added eqv for bitwise equality, and change eq to be arithmetic equalityazidar
2015-07-30Updated lots of tests so they pass. Found one bug in expand whensazidar
2015-07-29Finished supporting Chisel 2.0 Ref ChipAdam Izraelevitz
2015-07-29Add bigint support.Adam Izraelevitz
2015-07-28Integrated bigint. Mostly works, but getting "cast" error for make Test.Adam Izraelevitz
2015-07-14Added tests for clocks. Added remove scope and special chars passes. Added ↵azidar
tests. Made more tests pass
2015-07-14Added clock supportazidar
2015-07-14Pass most tests. The ones that do not pass are not expected to, yetazidar
2015-07-14Added chisel feedback to firrtl spec. Datapath_new triggers too large a ↵azidar
width error
2015-07-14Still partial commit, many tests pass. Many tests fail.azidar
2015-07-14In progress commitazidar
2015-06-12Major revisions to spec. Bumped to v0.1.2azidar
2015-06-04Fixed fir files so they correctly compile to verilog! Front-end needs to ↵azidar
generate as-SInt instead of convert, always. Added fast build to Makefile
2015-06-03Fixed verilog backend bugs. Passes ALU. Fails Datapathazidar
2015-06-02Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ↵azidar
low-firrtl syntax. Generates verilog that compiles, but is not correct
2015-06-02Added sequential/combinational memories. Started debugging verilog backend. ↵azidar
Added Long support so UInt(LARGENUMBER) works
2015-05-29Added custom pass. Does not correctly run, stanza just spins. Requires ↵azidar
debugging.
2015-05-27Added sequential memories. mem no longer exists, must declare either cmem or ↵azidar
smem. Added firrtl-gensym utility to generate a hashmap of names
2015-05-27Added external modules. Switched lower firrtl back to wire r; r := Register, ↵azidar
instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed
2015-05-26Added <>. Added additional checks for primops. Added new chisel3 files.azidar
2015-05-21Added pad pass, used for flo backendazidar
2015-05-20Added Pad pass to flo.stanza, which pads widths to make := and primops ↵azidar
strict. Have not tested this
2015-05-19Updated testsazidar
2015-05-18First pass at a Verilog Backend. Not tested, but compiles and generates ↵azidar
reasonable verilog. Requires inlining, future versions will instantiate modules
2015-05-18Big API Change. Pad is no longer supported. Widths of primops can be ↵azidar
flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters
2015-05-15Updated firrtl for its passes to be a bit more modular, and to enable ↵azidar
plugging in other backends. Also updated a lot of tests, but not all of them because its annoying.
2015-05-13Added source indicators from FIRRTL files. Pass in -p i to get them printed. ↵azidar
Should show up with check passes
2015-05-13Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bugazidar
2015-05-05Added a bunch of tests. In the middle of implementing check kinds and check ↵azidar
types. Does not compile
2015-05-04Added new Control.fir with reduced paddingazidar
2015-05-04Fixed bug where instance types were not loweredazidar
2015-05-04Updated stuffazidar
2015-05-04Fixed change where type of mux-ss was incorrectazidar
2015-05-02Added a infrastructure for check passes, and wrote a fewazidar
2015-05-02Now when expanding ConnectFrom/ToIndex, create a node for the index so it ↵azidar
isn't duplicated for all the whens
2015-05-01Bug fix. ExpWidth was improperly evaluated during simplify (not subtracting one)azidar
2015-05-01Fixed performance bug where PlusWidth, MinusWidth, and ExpWidth could be ↵azidar
simplified earlier, and also now have equal? defined so mMaxWidth doesn't blow up during width inference