Added pad pass, used for flo backend

11 files changed, 570 insertions, 836 deletions

diff --git a/test/chisel3/Control.fir b/test/chisel3/Control.fir
index 89c2ac13..2d109102 100644
--- a/test/chisel3/Control.fir
+++ b/test/chisel3/Control.fir
@@ -1,98 +1,96 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
-; CHECK: Done!
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
 
 circuit Control : 
   module Control : 
     output ctrl : {flip inst : UInt<32>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>, pc_sel : UInt<1>, inst_re : UInt<1>, flip stall : UInt<1>, data_re : UInt<1>, inst_type : UInt<1>, A_sel : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>}
     
-    node Y = UInt<1>(1)
-    node N = UInt<1>(0)
-    node T_831 = bit-and(UInt<32>(127), ctrl.inst)
-    node T_832 = eq(T_831, UInt<32>(55))
-    node T_833 = bit-and(UInt<32>(127), ctrl.inst)
-    node T_834 = eq(T_833, UInt<32>(23))
-    node T_835 = bit-and(UInt<32>(127), ctrl.inst)
-    node T_836 = eq(T_835, UInt<32>(111))
-    node T_837 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_838 = eq(T_837, UInt<32>(103))
-    node T_839 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_840 = eq(T_839, UInt<32>(99))
-    node T_841 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_842 = eq(T_841, UInt<32>(4195))
-    node T_843 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_844 = eq(T_843, UInt<32>(16483))
-    node T_845 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_846 = eq(T_845, UInt<32>(20579))
-    node T_847 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_848 = eq(T_847, UInt<32>(24675))
-    node T_849 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_850 = eq(T_849, UInt<32>(28771))
-    node T_851 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_852 = eq(T_851, UInt<32>(3))
-    node T_853 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_854 = eq(T_853, UInt<32>(4099))
-    node T_855 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_856 = eq(T_855, UInt<32>(8195))
-    node T_857 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_858 = eq(T_857, UInt<32>(16387))
-    node T_859 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_860 = eq(T_859, UInt<32>(20483))
-    node T_861 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_862 = eq(T_861, UInt<32>(35))
-    node T_863 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_864 = eq(T_863, UInt<32>(4131))
-    node T_865 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_866 = eq(T_865, UInt<32>(8227))
-    node T_867 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_868 = eq(T_867, UInt<32>(19))
-    node T_869 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_870 = eq(T_869, UInt<32>(8211))
-    node T_871 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_872 = eq(T_871, UInt<32>(12307))
-    node T_873 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_874 = eq(T_873, UInt<32>(16403))
-    node T_875 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_876 = eq(T_875, UInt<32>(24595))
-    node T_877 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_878 = eq(T_877, UInt<32>(28691))
+    node T_831 = bit-and(UInt<7>(127), ctrl.inst)
+    node T_832 = eq(T_831, UInt<6>(55))
+    node T_833 = bit-and(UInt<7>(127), ctrl.inst)
+    node T_834 = eq(T_833, UInt<5>(23))
+    node T_835 = bit-and(UInt<7>(127), ctrl.inst)
+    node T_836 = eq(T_835, UInt<7>(111))
+    node T_837 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_838 = eq(T_837, UInt<7>(103))
+    node T_839 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_840 = eq(T_839, UInt<7>(99))
+    node T_841 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_842 = eq(T_841, UInt<13>(4195))
+    node T_843 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_844 = eq(T_843, UInt<15>(16483))
+    node T_845 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_846 = eq(T_845, UInt<15>(20579))
+    node T_847 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_848 = eq(T_847, UInt<15>(24675))
+    node T_849 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_850 = eq(T_849, UInt<15>(28771))
+    node T_851 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_852 = eq(T_851, UInt<2>(3))
+    node T_853 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_854 = eq(T_853, UInt<13>(4099))
+    node T_855 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_856 = eq(T_855, UInt<14>(8195))
+    node T_857 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_858 = eq(T_857, UInt<15>(16387))
+    node T_859 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_860 = eq(T_859, UInt<15>(20483))
+    node T_861 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_862 = eq(T_861, UInt<6>(35))
+    node T_863 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_864 = eq(T_863, UInt<13>(4131))
+    node T_865 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_866 = eq(T_865, UInt<14>(8227))
+    node T_867 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_868 = eq(T_867, UInt<5>(19))
+    node T_869 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_870 = eq(T_869, UInt<14>(8211))
+    node T_871 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_872 = eq(T_871, UInt<14>(12307))
+    node T_873 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_874 = eq(T_873, UInt<15>(16403))
+    node T_875 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_876 = eq(T_875, UInt<15>(24595))
+    node T_877 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_878 = eq(T_877, UInt<15>(28691))
     node T_879 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_880 = eq(T_879, UInt<32>(4115))
+    node T_880 = eq(T_879, UInt<13>(4115))
     node T_881 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_882 = eq(T_881, UInt<32>(20499))
+    node T_882 = eq(T_881, UInt<15>(20499))
     node T_883 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_884 = eq(T_883, UInt<32>(1073762323))
+    node T_884 = eq(T_883, UInt<31>(1073762323))
     node T_885 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_886 = eq(T_885, UInt<32>(51))
+    node T_886 = eq(T_885, UInt<6>(51))
     node T_887 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_888 = eq(T_887, UInt<32>(1073741875))
+    node T_888 = eq(T_887, UInt<31>(1073741875))
     node T_889 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_890 = eq(T_889, UInt<32>(4147))
+    node T_890 = eq(T_889, UInt<13>(4147))
     node T_891 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_892 = eq(T_891, UInt<32>(8243))
+    node T_892 = eq(T_891, UInt<14>(8243))
     node T_893 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_894 = eq(T_893, UInt<32>(12339))
+    node T_894 = eq(T_893, UInt<14>(12339))
     node T_895 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_896 = eq(T_895, UInt<32>(16435))
+    node T_896 = eq(T_895, UInt<15>(16435))
     node T_897 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_898 = eq(T_897, UInt<32>(20531))
+    node T_898 = eq(T_897, UInt<15>(20531))
     node T_899 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_900 = eq(T_899, UInt<32>(1073762355))
+    node T_900 = eq(T_899, UInt<31>(1073762355))
     node T_901 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_902 = eq(T_901, UInt<32>(24627))
+    node T_902 = eq(T_901, UInt<15>(24627))
     node T_903 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_904 = eq(T_903, UInt<32>(28723))
-    node T_905 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_906 = eq(T_905, UInt<32>(4211))
-    node T_907 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_908 = eq(T_907, UInt<32>(8307))
-    node T_909 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_910 = eq(T_909, UInt<32>(12403))
-    node T_911 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_912 = eq(T_911, UInt<32>(20595))
-    node T_913 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_914 = eq(T_913, UInt<32>(24691))
-    node T_915 = bit-and(UInt<32>(28799), ctrl.inst)
-    node T_916 = eq(T_915, UInt<32>(28787))
+    node T_904 = eq(T_903, UInt<15>(28723))
+    node T_905 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_906 = eq(T_905, UInt<13>(4211))
+    node T_907 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_908 = eq(T_907, UInt<14>(8307))
+    node T_909 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_910 = eq(T_909, UInt<14>(12403))
+    node T_911 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_912 = eq(T_911, UInt<15>(20595))
+    node T_913 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_914 = eq(T_913, UInt<15>(24691))
+    node T_915 = bit-and(UInt<15>(28799), ctrl.inst)
+    node T_916 = eq(T_915, UInt<15>(28787))
     node T_917 = mux(T_916, UInt<1>(0), UInt<1>(0))
     node T_918 = mux(T_914, UInt<1>(0), T_917)
     node T_919 = mux(T_912, UInt<1>(0), T_918)
@@ -351,49 +349,49 @@ circuit Control :
     node T_1172 = mux(T_836, UInt<3>(7), T_1171)
     node T_1173 = mux(T_834, UInt<3>(7), T_1172)
     node T_1174 = mux(T_832, UInt<3>(7), T_1173)
-    node T_1175 = mux(T_916, N, N)
-    node T_1176 = mux(T_914, N, T_1175)
-    node T_1177 = mux(T_912, N, T_1176)
-    node T_1178 = mux(T_910, N, T_1177)
-    node T_1179 = mux(T_908, N, T_1178)
-    node T_1180 = mux(T_906, N, T_1179)
-    node T_1181 = mux(T_904, N, T_1180)
-    node T_1182 = mux(T_902, N, T_1181)
-    node T_1183 = mux(T_900, N, T_1182)
-    node T_1184 = mux(T_898, N, T_1183)
-    node T_1185 = mux(T_896, N, T_1184)
-    node T_1186 = mux(T_894, N, T_1185)
-    node T_1187 = mux(T_892, N, T_1186)
-    node T_1188 = mux(T_890, N, T_1187)
-    node T_1189 = mux(T_888, N, T_1188)
-    node T_1190 = mux(T_886, N, T_1189)
-    node T_1191 = mux(T_884, N, T_1190)
-    node T_1192 = mux(T_882, N, T_1191)
-    node T_1193 = mux(T_880, N, T_1192)
-    node T_1194 = mux(T_878, N, T_1193)
-    node T_1195 = mux(T_876, N, T_1194)
-    node T_1196 = mux(T_874, N, T_1195)
-    node T_1197 = mux(T_872, N, T_1196)
-    node T_1198 = mux(T_870, N, T_1197)
-    node T_1199 = mux(T_868, N, T_1198)
-    node T_1200 = mux(T_866, N, T_1199)
-    node T_1201 = mux(T_864, N, T_1200)
-    node T_1202 = mux(T_862, N, T_1201)
-    node T_1203 = mux(T_860, N, T_1202)
-    node T_1204 = mux(T_858, N, T_1203)
-    node T_1205 = mux(T_856, N, T_1204)
-    node T_1206 = mux(T_854, N, T_1205)
-    node T_1207 = mux(T_852, N, T_1206)
-    node T_1208 = mux(T_850, N, T_1207)
-    node T_1209 = mux(T_848, N, T_1208)
-    node T_1210 = mux(T_846, N, T_1209)
-    node T_1211 = mux(T_844, N, T_1210)
-    node T_1212 = mux(T_842, N, T_1211)
-    node T_1213 = mux(T_840, N, T_1212)
-    node T_1214 = mux(T_838, Y, T_1213)
-    node T_1215 = mux(T_836, Y, T_1214)
-    node T_1216 = mux(T_834, N, T_1215)
-    node T_1217 = mux(T_832, N, T_1216)
+    node T_1175 = mux(T_916, UInt<1>(0), UInt<1>(0))
+    node T_1176 = mux(T_914, UInt<1>(0), T_1175)
+    node T_1177 = mux(T_912, UInt<1>(0), T_1176)
+    node T_1178 = mux(T_910, UInt<1>(0), T_1177)
+    node T_1179 = mux(T_908, UInt<1>(0), T_1178)
+    node T_1180 = mux(T_906, UInt<1>(0), T_1179)
+    node T_1181 = mux(T_904, UInt<1>(0), T_1180)
+    node T_1182 = mux(T_902, UInt<1>(0), T_1181)
+    node T_1183 = mux(T_900, UInt<1>(0), T_1182)
+    node T_1184 = mux(T_898, UInt<1>(0), T_1183)
+    node T_1185 = mux(T_896, UInt<1>(0), T_1184)
+    node T_1186 = mux(T_894, UInt<1>(0), T_1185)
+    node T_1187 = mux(T_892, UInt<1>(0), T_1186)
+    node T_1188 = mux(T_890, UInt<1>(0), T_1187)
+    node T_1189 = mux(T_888, UInt<1>(0), T_1188)
+    node T_1190 = mux(T_886, UInt<1>(0), T_1189)
+    node T_1191 = mux(T_884, UInt<1>(0), T_1190)
+    node T_1192 = mux(T_882, UInt<1>(0), T_1191)
+    node T_1193 = mux(T_880, UInt<1>(0), T_1192)
+    node T_1194 = mux(T_878, UInt<1>(0), T_1193)
+    node T_1195 = mux(T_876, UInt<1>(0), T_1194)
+    node T_1196 = mux(T_874, UInt<1>(0), T_1195)
+    node T_1197 = mux(T_872, UInt<1>(0), T_1196)
+    node T_1198 = mux(T_870, UInt<1>(0), T_1197)
+    node T_1199 = mux(T_868, UInt<1>(0), T_1198)
+    node T_1200 = mux(T_866, UInt<1>(0), T_1199)
+    node T_1201 = mux(T_864, UInt<1>(0), T_1200)
+    node T_1202 = mux(T_862, UInt<1>(0), T_1201)
+    node T_1203 = mux(T_860, UInt<1>(0), T_1202)
+    node T_1204 = mux(T_858, UInt<1>(0), T_1203)
+    node T_1205 = mux(T_856, UInt<1>(0), T_1204)
+    node T_1206 = mux(T_854, UInt<1>(0), T_1205)
+    node T_1207 = mux(T_852, UInt<1>(0), T_1206)
+    node T_1208 = mux(T_850, UInt<1>(0), T_1207)
+    node T_1209 = mux(T_848, UInt<1>(0), T_1208)
+    node T_1210 = mux(T_846, UInt<1>(0), T_1209)
+    node T_1211 = mux(T_844, UInt<1>(0), T_1210)
+    node T_1212 = mux(T_842, UInt<1>(0), T_1211)
+    node T_1213 = mux(T_840, UInt<1>(0), T_1212)
+    node T_1214 = mux(T_838, UInt<1>(1), T_1213)
+    node T_1215 = mux(T_836, UInt<1>(1), T_1214)
+    node T_1216 = mux(T_834, UInt<1>(0), T_1215)
+    node T_1217 = mux(T_832, UInt<1>(0), T_1216)
     node T_1218 = mux(T_916, UInt<2>(3), UInt<2>(3))
     node T_1219 = mux(T_914, UInt<2>(3), T_1218)
     node T_1220 = mux(T_912, UInt<2>(3), T_1219)
@@ -523,49 +521,49 @@ circuit Control :
     node T_1344 = mux(T_836, UInt<2>(2), T_1343)
     node T_1345 = mux(T_834, UInt<2>(0), T_1344)
     node T_1346 = mux(T_832, UInt<2>(0), T_1345)
-    node T_1347 = mux(T_916, N, N)
-    node T_1348 = mux(T_914, N, T_1347)
-    node T_1349 = mux(T_912, N, T_1348)
-    node T_1350 = mux(T_910, N, T_1349)
-    node T_1351 = mux(T_908, N, T_1350)
-    node T_1352 = mux(T_906, N, T_1351)
-    node T_1353 = mux(T_904, Y, T_1352)
-    node T_1354 = mux(T_902, Y, T_1353)
-    node T_1355 = mux(T_900, Y, T_1354)
-    node T_1356 = mux(T_898, Y, T_1355)
-    node T_1357 = mux(T_896, Y, T_1356)
-    node T_1358 = mux(T_894, Y, T_1357)
-    node T_1359 = mux(T_892, Y, T_1358)
-    node T_1360 = mux(T_890, Y, T_1359)
-    node T_1361 = mux(T_888, Y, T_1360)
-    node T_1362 = mux(T_886, Y, T_1361)
-    node T_1363 = mux(T_884, Y, T_1362)
-    node T_1364 = mux(T_882, Y, T_1363)
-    node T_1365 = mux(T_880, Y, T_1364)
-    node T_1366 = mux(T_878, Y, T_1365)
-    node T_1367 = mux(T_876, Y, T_1366)
-    node T_1368 = mux(T_874, Y, T_1367)
-    node T_1369 = mux(T_872, Y, T_1368)
-    node T_1370 = mux(T_870, Y, T_1369)
-    node T_1371 = mux(T_868, Y, T_1370)
-    node T_1372 = mux(T_866, N, T_1371)
-    node T_1373 = mux(T_864, N, T_1372)
-    node T_1374 = mux(T_862, N, T_1373)
-    node T_1375 = mux(T_860, Y, T_1374)
-    node T_1376 = mux(T_858, Y, T_1375)
-    node T_1377 = mux(T_856, Y, T_1376)
-    node T_1378 = mux(T_854, Y, T_1377)
-    node T_1379 = mux(T_852, Y, T_1378)
-    node T_1380 = mux(T_850, N, T_1379)
-    node T_1381 = mux(T_848, N, T_1380)
-    node T_1382 = mux(T_846, N, T_1381)
-    node T_1383 = mux(T_844, N, T_1382)
-    node T_1384 = mux(T_842, N, T_1383)
-    node T_1385 = mux(T_840, N, T_1384)
-    node T_1386 = mux(T_838, Y, T_1385)
-    node T_1387 = mux(T_836, Y, T_1386)
-    node T_1388 = mux(T_834, Y, T_1387)
-    node T_1389 = mux(T_832, Y, T_1388)
+    node T_1347 = mux(T_916, UInt<1>(0), UInt<1>(0))
+    node T_1348 = mux(T_914, UInt<1>(0), T_1347)
+    node T_1349 = mux(T_912, UInt<1>(0), T_1348)
+    node T_1350 = mux(T_910, UInt<1>(0), T_1349)
+    node T_1351 = mux(T_908, UInt<1>(0), T_1350)
+    node T_1352 = mux(T_906, UInt<1>(0), T_1351)
+    node T_1353 = mux(T_904, UInt<1>(1), T_1352)
+    node T_1354 = mux(T_902, UInt<1>(1), T_1353)
+    node T_1355 = mux(T_900, UInt<1>(1), T_1354)
+    node T_1356 = mux(T_898, UInt<1>(1), T_1355)
+    node T_1357 = mux(T_896, UInt<1>(1), T_1356)
+    node T_1358 = mux(T_894, UInt<1>(1), T_1357)
+    node T_1359 = mux(T_892, UInt<1>(1), T_1358)
+    node T_1360 = mux(T_890, UInt<1>(1), T_1359)
+    node T_1361 = mux(T_888, UInt<1>(1), T_1360)
+    node T_1362 = mux(T_886, UInt<1>(1), T_1361)
+    node T_1363 = mux(T_884, UInt<1>(1), T_1362)
+    node T_1364 = mux(T_882, UInt<1>(1), T_1363)
+    node T_1365 = mux(T_880, UInt<1>(1), T_1364)
+    node T_1366 = mux(T_878, UInt<1>(1), T_1365)
+    node T_1367 = mux(T_876, UInt<1>(1), T_1366)
+    node T_1368 = mux(T_874, UInt<1>(1), T_1367)
+    node T_1369 = mux(T_872, UInt<1>(1), T_1368)
+    node T_1370 = mux(T_870, UInt<1>(1), T_1369)
+    node T_1371 = mux(T_868, UInt<1>(1), T_1370)
+    node T_1372 = mux(T_866, UInt<1>(0), T_1371)
+    node T_1373 = mux(T_864, UInt<1>(0), T_1372)
+    node T_1374 = mux(T_862, UInt<1>(0), T_1373)
+    node T_1375 = mux(T_860, UInt<1>(1), T_1374)
+    node T_1376 = mux(T_858, UInt<1>(1), T_1375)
+    node T_1377 = mux(T_856, UInt<1>(1), T_1376)
+    node T_1378 = mux(T_854, UInt<1>(1), T_1377)
+    node T_1379 = mux(T_852, UInt<1>(1), T_1378)
+    node T_1380 = mux(T_850, UInt<1>(0), T_1379)
+    node T_1381 = mux(T_848, UInt<1>(0), T_1380)
+    node T_1382 = mux(T_846, UInt<1>(0), T_1381)
+    node T_1383 = mux(T_844, UInt<1>(0), T_1382)
+    node T_1384 = mux(T_842, UInt<1>(0), T_1383)
+    node T_1385 = mux(T_840, UInt<1>(0), T_1384)
+    node T_1386 = mux(T_838, UInt<1>(1), T_1385)
+    node T_1387 = mux(T_836, UInt<1>(1), T_1386)
+    node T_1388 = mux(T_834, UInt<1>(1), T_1387)
+    node T_1389 = mux(T_832, UInt<1>(1), T_1388)
     node T_1390 = mux(T_916, UInt<2>(3), UInt<2>(0))
     node T_1391 = mux(T_914, UInt<2>(2), T_1390)
     node T_1392 = mux(T_912, UInt<2>(1), T_1391)
@@ -614,8 +612,7 @@ circuit Control :
     reg st_type : UInt<2>
     reg ld_type : UInt<3>
     reg wb_sel : UInt<2>
-    wire T_1433 : UInt<1>
-    T_1433 := T_1389
+    node T_1433 = bit(T_1389, 0)
     reg wb_en : UInt<1>
     reg csr_cmd : UInt<2>
     ctrl.pc_sel := T_959
@@ -624,8 +621,7 @@ circuit Control :
     node T_1436 = bit-and(T_1434, T_1435)
     ctrl.inst_re := T_1436
     node T_1437 = neq(T_1303, UInt<3>(7))
-    wire T_1438 : UInt<1>
-    T_1438 := T_1217
+    node T_1438 = bit(T_1217, 0)
     node T_1439 = bit-or(T_1437, T_1438)
     node T_1440 = mux(T_1439, UInt<1>(1), UInt<1>(0))
     ctrl.inst_type := T_1440
@@ -640,8 +636,7 @@ circuit Control :
       st_type := ctrl.st_type
       ld_type := T_1303
       wb_sel := T_1346
-      wire T_1442 : UInt<1>
-      T_1442 := T_1389
+      node T_1442 = bit(T_1389, 0)
       wb_en := T_1442
       csr_cmd := T_1432
     node T_1443 = neq(ctrl.ld_type, UInt<3>(7))
diff --git a/test/chisel3/Datapath.fir b/test/chisel3/Datapath.fir
index 0727d53e..ef62df98 100644
--- a/test/chisel3/Datapath.fir
+++ b/test/chisel3/Datapath.fir
@@ -1,5 +1,5 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p cdi | tee %s.out | FileCheck %s
-; CHECK: Done!
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
 
 circuit Datapath : 
   module ALU : 
@@ -9,60 +9,53 @@ circuit Datapath :
     input A : UInt<32>
     input alu_op : UInt<4>
     
-    node T_431 = bits(B, 4, 0)
-    wire shamt : UInt<5>
-    shamt := T_431
-    node T_432 = add-wrap(A, B)
-    node T_433 = sub-wrap(A, B)
-    wire T_434 : SInt<32>
-    T_434 := A
-    node T_435 = dshr(T_434, shamt)
-    wire T_436 : UInt<32>
-    T_436 := T_435
-    node T_437 = dshr(A, shamt)
-    node T_438 = dshl(A, shamt)
-    node T_439 = bits(T_438, 31, 0)
-    wire T_440 : SInt<32>
-    T_440 := A
-    wire T_441 : SInt<32>
-    T_441 := B
-    node T_442 = lt(T_440, T_441)
-    wire T_443 : UInt<1>
-    T_443 := T_442
-    node T_444 = lt(A, B)
-    wire T_445 : UInt<1>
-    T_445 := T_444
-    node T_446 = bit-and(A, B)
-    node T_447 = bit-or(A, B)
-    node T_448 = bit-xor(A, B)
-    node T_449 = eq(UInt<4>(10), alu_op)
-    node T_450 = mux(T_449, A, B)
-    node T_451 = eq(UInt<4>(4), alu_op)
-    node T_452 = mux(T_451, T_448, T_450)
-    node T_453 = eq(UInt<4>(3), alu_op)
-    node T_454 = mux(T_453, T_447, T_452)
-    node T_455 = eq(UInt<4>(2), alu_op)
-    node T_456 = mux(T_455, T_446, T_454)
-    node T_457 = eq(UInt<4>(7), alu_op)
-    node T_458 = mux(T_457, Pad(T_445,32), T_456)
-    node T_459 = eq(UInt<4>(5), alu_op)
-    node T_460 = mux(T_459, Pad(T_443,32), T_458)
-    node T_461 = eq(UInt<4>(6), alu_op)
-    node T_462 = mux(T_461, T_439, T_460)
-    node T_463 = eq(UInt<4>(8), alu_op)
-    node T_464 = mux(T_463, T_437, T_462)
-    node T_465 = eq(UInt<4>(9), alu_op)
-    node T_466 = mux(T_465, T_436, T_464)
-    node T_467 = eq(UInt<4>(1), alu_op)
-    node T_468 = mux(T_467, T_433, T_466)
-    node T_469 = eq(UInt<4>(0), alu_op)
-    node T_470 = mux(T_469, T_432, T_468)
-    out := T_470
-    node T_471 = bit(alu_op, 0)
-    node T_472 = sub-wrap(UInt<32>(0), B)
-    node T_473 = mux(T_471, T_472, B)
-    node T_474 = add-wrap(A, T_473)
-    sum := T_474
+    node shamt = bits(B, 4, 0)
+    node T_433 = add-wrap(A, B)
+    node T_434 = sub-wrap(A, B)
+    node T_435 = convert(A)
+    node T_436 = dshr(T_435, shamt)
+    node T_437 = as-UInt(T_436)
+    node T_438 = dshr(A, shamt)
+    node T_439 = dshl(A, shamt)
+    node T_440 = bits(T_439, 31, 0)
+    node T_441 = convert(A)
+    node T_442 = convert(B)
+    node T_443 = lt(T_441, T_442)
+    node T_444 = as-UInt(T_443)
+    node T_445 = lt(A, B)
+    node T_446 = as-UInt(T_445)
+    node T_447 = bit-and(A, B)
+    node T_448 = bit-or(A, B)
+    node T_449 = bit-xor(A, B)
+    node T_450 = eq(UInt<4>(10), alu_op)
+    node T_451 = mux(T_450, A, B)
+    node T_452 = eq(UInt<4>(4), alu_op)
+    node T_453 = mux(T_452, T_449, T_451)
+    node T_454 = eq(UInt<4>(3), alu_op)
+    node T_455 = mux(T_454, T_448, T_453)
+    node T_456 = eq(UInt<4>(2), alu_op)
+    node T_457 = mux(T_456, T_447, T_455)
+    node T_458 = eq(UInt<4>(7), alu_op)
+    node T_459 = mux(T_458, T_446, T_457)
+    node T_460 = eq(UInt<4>(5), alu_op)
+    node T_461 = mux(T_460, T_444, T_459)
+    node T_462 = eq(UInt<4>(6), alu_op)
+    node T_463 = mux(T_462, T_440, T_461)
+    node T_464 = eq(UInt<4>(8), alu_op)
+    node T_465 = mux(T_464, T_438, T_463)
+    node T_466 = eq(UInt<4>(9), alu_op)
+    node T_467 = mux(T_466, T_437, T_465)
+    node T_468 = eq(UInt<4>(1), alu_op)
+    node T_469 = mux(T_468, T_434, T_467)
+    node T_470 = eq(UInt<4>(0), alu_op)
+    node oot = mux(T_470, T_433, T_469)
+    node T_471 = bits(oot, 31, 0)
+    out := T_471
+    node T_472 = bit(alu_op, 0)
+    node T_473 = sub-wrap(UInt<1>(0), B)
+    node T_474 = mux(T_472, T_473, B)
+    node T_475 = add-wrap(A, T_474)
+    sum := T_475
   module BrCond : 
     input rs1 : UInt<32>
     input rs2 : UInt<32>
@@ -71,34 +64,30 @@ circuit Datapath :
     
     node eq = eq(rs1, rs2)
     node neq = bit-not(eq)
-    wire T_475 : SInt<32>
-    T_475 := rs1
-    wire T_476 : SInt<32>
-    T_476 := rs2
-    node lt = lt(T_475, T_476)
+    node T_476 = convert(rs1)
+    node T_477 = convert(rs2)
+    node lt = lt(T_476, T_477)
     node ge = bit-not(lt)
     node ltu = lt(rs1, rs2)
     node geu = bit-not(ltu)
-    node T_477 = UInt<1>(1)
-    node T_478 = UInt<1>(0)
-    node T_479 = eq(br_type, UInt<3>(2))
-    node T_480 = bit-and(T_479, eq)
-    node T_481 = eq(br_type, UInt<3>(6))
-    node T_482 = bit-and(T_481, neq)
-    node T_483 = bit-or(T_480, T_482)
-    node T_484 = eq(br_type, UInt<3>(1))
-    node T_485 = bit-and(T_484, lt)
-    node T_486 = bit-or(T_483, T_485)
-    node T_487 = eq(br_type, UInt<3>(5))
-    node T_488 = bit-and(T_487, ge)
-    node T_489 = bit-or(T_486, T_488)
-    node T_490 = eq(br_type, UInt<3>(0))
-    node T_491 = bit-and(T_490, ltu)
-    node T_492 = bit-or(T_489, T_491)
-    node T_493 = eq(br_type, UInt<3>(4))
-    node T_494 = bit-and(T_493, geu)
-    node T_495 = bit-or(T_492, T_494)
-    taken := T_495
+    node T_478 = eq(br_type, UInt<3>(2))
+    node T_479 = bit-and(T_478, eq)
+    node T_480 = eq(br_type, UInt<3>(6))
+    node T_481 = bit-and(T_480, neq)
+    node T_482 = bit-or(T_479, T_481)
+    node T_483 = eq(br_type, UInt<3>(1))
+    node T_484 = bit-and(T_483, lt)
+    node T_485 = bit-or(T_482, T_484)
+    node T_486 = eq(br_type, UInt<3>(5))
+    node T_487 = bit-and(T_486, ge)
+    node T_488 = bit-or(T_485, T_487)
+    node T_489 = eq(br_type, UInt<3>(0))
+    node T_490 = bit-and(T_489, ltu)
+    node T_491 = bit-or(T_488, T_490)
+    node T_492 = eq(br_type, UInt<3>(4))
+    node T_493 = bit-and(T_492, geu)
+    node T_494 = bit-or(T_491, T_493)
+    taken := T_494
   module RegFile : 
     input raddr1 : UInt<5>
     input raddr2 : UInt<5>
@@ -109,83 +98,76 @@ circuit Datapath :
     input wdata : UInt<32>
     
     mem regs : UInt<32>[32]
-    node T_496 = eq(raddr1, UInt<5>(0))
-    node T_497 = bit-not(T_496)
-    accessor T_498 = regs[raddr1]
-    node T_499 = mux(T_497, T_498, UInt<32>(0))
-    rdata1 := T_499
-    node T_500 = eq(raddr2, UInt<5>(0))
-    node T_501 = bit-not(T_500)
-    accessor T_502 = regs[raddr2]
-    node T_503 = mux(T_501, T_502, UInt<32>(0))
-    rdata2 := T_503
-    node T_504 = eq(waddr, UInt<5>(0))
-    node T_505 = bit-not(T_504)
-    node T_506 = bit-and(wen, T_505)
-    when T_506 : 
-      accessor T_507 = regs[waddr]
-      T_507 := wdata
+    node T_495 = eq(raddr1, UInt<1>(0))
+    node T_496 = bit-not(T_495)
+    accessor T_497 = regs[raddr1]
+    node T_498 = mux(T_496, T_497, UInt<1>(0))
+    rdata1 := T_498
+    node T_499 = eq(raddr2, UInt<1>(0))
+    node T_500 = bit-not(T_499)
+    accessor T_501 = regs[raddr2]
+    node T_502 = mux(T_500, T_501, UInt<1>(0))
+    rdata2 := T_502
+    node T_503 = eq(waddr, UInt<1>(0))
+    node T_504 = bit-not(T_503)
+    node T_505 = bit-and(wen, T_504)
+    when T_505 : 
+      accessor T_506 = regs[waddr]
+      T_506 := wdata
   module ImmGenWire : 
     output out : UInt<32>
     input inst : UInt<32>
     input sel : UInt<3>
     
-    node T_508 = bits(inst, 31, 20)
-    wire Iimm : SInt<12>
-    Iimm := T_508
-    node T_509 = bits(inst, 31, 25)
-    node T_510 = bits(inst, 11, 7)
-    node T_511 = cat(T_509, T_510)
-    wire Simm : SInt<12>
-    Simm := T_511
-    node T_512 = bit(inst, 31)
-    node T_513 = bit(inst, 7)
-    node T_514 = bits(inst, 30, 25)
-    node T_515 = bits(inst, 11, 8)
-    node T_516 = cat(T_512, T_513)
-    node T_517 = cat(T_515, UInt<1>(0))
-    node T_518 = cat(T_514, T_517)
-    node T_519 = cat(T_516, T_518)
-    wire Bimm : SInt<1>
-    Bimm := T_519
-    node T_520 = bits(inst, 31, 12)
-    node T_521 = cat(T_520, UInt<12>(0))
-    wire Uimm : SInt<32>
-    Uimm := T_521
-    node T_522 = bit(inst, 31)
-    node T_523 = bits(inst, 19, 12)
-    node T_524 = bit(inst, 20)
-    node T_525 = bits(inst, 30, 25)
-    node T_526 = bits(inst, 24, 21)
-    node T_527 = cat(T_523, T_524)
-    node T_528 = cat(T_522, T_527)
-    node T_529 = cat(T_526, UInt<1>(0))
-    node T_530 = cat(T_525, T_529)
-    node T_531 = cat(T_528, T_530)
-    wire Jimm : SInt<1>
-    Jimm := T_531
-    node T_532 = bits(inst, 19, 15)
-    wire T_533 : UInt<5>
-    T_533 := T_532
-    node T_534 = Pad(T_533, 32)
-    wire Zimm : SInt<32>
-    Zimm := T_534
-    node T_535 = eq(UInt<3>(3), sel)
-    node T_536 = mux(T_535, Pad(Jimm,32), Zimm)
-    node T_537 = eq(UInt<3>(2), sel)
-    node T_538 = mux(T_537, Uimm, T_536)
-    node T_539 = eq(UInt<3>(4), sel)
-    node T_540 = mux(T_539, Pad(Bimm,32), T_538)
-    node T_541 = eq(UInt<3>(1), sel)
-    node T_542 = mux(T_541, Pad(Simm,32), T_540)
-    node T_543 = eq(UInt<3>(0), sel)
-    node T_544 = mux(T_543, Pad(Iimm,32), T_542)
-    out := T_544
+    node T_507 = bits(inst, 31, 20)
+    node Iimm = convert(T_507)
+    node T_508 = bits(inst, 31, 25)
+    node T_509 = bits(inst, 11, 7)
+    node T_510 = cat(T_508, T_509)
+    node Simm = convert(T_510)
+    node T_511 = bit(inst, 31)
+    node T_512 = bit(inst, 7)
+    node T_513 = bits(inst, 30, 25)
+    node T_514 = bits(inst, 11, 8)
+    node T_515 = cat(T_511, T_512)
+    node T_516 = cat(T_514, UInt<1>(0))
+    node T_517 = cat(T_513, T_516)
+    node T_518 = cat(T_515, T_517)
+    node Bimm = convert(T_518)
+    node T_519 = bits(inst, 31, 12)
+    node T_520 = cat(T_519, UInt<12>(0))
+    node Uimm = convert(T_520)
+    node T_521 = bit(inst, 31)
+    node T_522 = bits(inst, 19, 12)
+    node T_523 = bit(inst, 20)
+    node T_524 = bits(inst, 30, 25)
+    node T_525 = bits(inst, 24, 21)
+    node T_526 = cat(T_522, T_523)
+    node T_527 = cat(T_521, T_526)
+    node T_528 = cat(T_525, UInt<1>(0))
+    node T_529 = cat(T_524, T_528)
+    node T_530 = cat(T_527, T_529)
+    node Jimm = convert(T_530)
+    node T_531 = bits(inst, 19, 15)
+    node T_532 = pad(T_531, 32)
+    node Zimm = convert(T_532)
+    node T_533 = eq(UInt<3>(3), sel)
+    node T_534 = mux(T_533, Jimm, Zimm)
+    node T_535 = eq(UInt<3>(2), sel)
+    node T_536 = mux(T_535, Uimm, T_534)
+    node T_537 = eq(UInt<3>(4), sel)
+    node T_538 = mux(T_537, Bimm, T_536)
+    node T_539 = eq(UInt<3>(1), sel)
+    node T_540 = mux(T_539, Simm, T_538)
+    node T_541 = eq(UInt<3>(0), sel)
+    node T_542 = mux(T_541, Iimm, T_540)
+    node T_543 = as-UInt(T_542)
+    out := T_543
   module CSR : 
-    output host : {status : UInt<32>, flip hid : UInt<1>, tohost : UInt<32>}
+    output host : {status : UInt<32>, tohost : UInt<32>, flip hid : UInt<1>}
     input src : UInt<32>
-    output data : UInt<32>
     input cmd : UInt<2>
+    output data : UInt<32>
     input addr : UInt<12>
     
     reg reg_tohost : UInt<32>
@@ -194,54 +176,52 @@ circuit Datapath :
     on-reset reg_status := UInt<32>(0)
     host.tohost := reg_tohost
     host.status := reg_status
-    node T_545 = eq(UInt<12>(1291), addr)
-    node T_546 = mux(T_545, host.hid, UInt<1>(0))
-    node T_547 = eq(UInt<12>(1290), addr)
-    node T_548 = mux(T_547, reg_status, Pad(T_546,32))
-    node T_549 = eq(UInt<12>(1310), addr)
-    node T_550 = mux(T_549, reg_tohost, T_548)
-    wire T_551 : UInt<32>
-    T_551 := T_550
-    data := T_551
-    node T_552 = eq(cmd, UInt<2>(1))
-    when T_552 : 
-      node T_553 = eq(addr, UInt<12>(1310))
-      when T_553 : reg_tohost := src
-      node T_554 = eq(addr, UInt<12>(1290))
-      when T_554 : reg_status := src
-    node T_555 = eq(cmd, UInt<2>(2))
-    node T_556 = neq(src, UInt<32>(0))
-    node T_557 = bit-and(T_555, T_556)
-    when T_557 : 
-      node T_558 = eq(addr, UInt<12>(1310))
-      when T_558 : 
-        node T_559 = dshl(UInt<1>(1), src)
-        node T_560 = bit-or(data, Pad(T_559,32))
-        reg_tohost := T_560
-      node T_561 = eq(addr, UInt<12>(1290))
-      when T_561 : 
-        node T_562 = dshl(UInt<1>(1), src)
-        node T_563 = bit-or(data, Pad(T_562,32))
-        reg_status := T_563
-    node T_564 = eq(cmd, UInt<2>(3))
-    node T_565 = neq(src, UInt<32>(0))
-    node T_566 = bit-and(T_564, T_565)
-    when T_566 : 
-      node T_567 = eq(addr, UInt<12>(1310))
-      when T_567 : 
-        node T_568 = dshl(UInt<1>(0), src)
-        node T_569 = bit-and(data, Pad(T_568,32))
-        reg_tohost := T_569
-      node T_570 = eq(addr, UInt<12>(1290))
-      when T_570 : 
-        node T_571 = dshl(UInt<1>(0), src)
-        node T_572 = bit-and(data, Pad(T_571,32))
-        reg_status := T_572
+    node T_544 = eq(UInt<12>(1291), addr)
+    node T_545 = mux(T_544, host.hid, UInt<1>(0))
+    node T_546 = eq(UInt<12>(1290), addr)
+    node T_547 = mux(T_546, reg_status, T_545)
+    node T_548 = eq(UInt<12>(1310), addr)
+    node T_549 = mux(T_548, reg_tohost, T_547)
+    data := T_549
+    node T_550 = eq(cmd, UInt<2>(1))
+    when T_550 : 
+      node T_551 = eq(addr, UInt<12>(1310))
+      when T_551 : reg_tohost := src
+      node T_552 = eq(addr, UInt<12>(1290))
+      when T_552 : reg_status := src
+    node T_553 = eq(cmd, UInt<2>(2))
+    node T_554 = neq(src, UInt<1>(0))
+    node T_555 = bit-and(T_553, T_554)
+    when T_555 : 
+      node T_556 = eq(addr, UInt<12>(1310))
+      when T_556 : 
+        node T_557 = dshl(UInt<1>(1), src)
+        node T_558 = bit-or(data, T_557)
+        reg_tohost := T_558
+      node T_559 = eq(addr, UInt<12>(1290))
+      when T_559 : 
+        node T_560 = dshl(UInt<1>(1), src)
+        node T_561 = bit-or(data, T_560)
+        reg_status := T_561
+    node T_562 = eq(cmd, UInt<2>(3))
+    node T_563 = neq(src, UInt<1>(0))
+    node T_564 = bit-and(T_562, T_563)
+    when T_564 : 
+      node T_565 = eq(addr, UInt<12>(1310))
+      when T_565 : 
+        node T_566 = dshl(UInt<1>(0), src)
+        node T_567 = bit-and(data, T_566)
+        reg_tohost := T_567
+      node T_568 = eq(addr, UInt<12>(1290))
+      when T_568 : 
+        node T_569 = dshl(UInt<1>(0), src)
+        node T_570 = bit-and(data, T_569)
+        reg_status := T_570
   module Datapath : 
-    output host : {status : UInt<32>, flip hid : UInt<1>, tohost : UInt<32>}
+    output host : {status : UInt<32>, tohost : UInt<32>, flip hid : UInt<1>}
     input ctrl : {flip inst : UInt<32>, pc_sel : UInt<1>, inst_type : UInt<1>, inst_re : UInt<1>, flip stall : UInt<1>, imm_sel : UInt<3>, wb_en : UInt<1>, wb_sel : UInt<2>, A_sel : UInt<1>, B_sel : UInt<1>, alu_op : UInt<4>, br_type : UInt<3>, data_re : UInt<1>, st_type : UInt<2>, ld_type : UInt<3>, csr_cmd : UInt<2>}
-    output icache : {re : UInt<1>, addr : UInt<32>, we : UInt<4>, din : UInt<32>, flip dout : UInt<32>}
-    output dcache : {re : UInt<1>, addr : UInt<32>, we : UInt<4>, din : UInt<32>, flip dout : UInt<32>}
+    output icache : {re : UInt<1>, flip dout : UInt<32>, we : UInt<4>, addr : UInt<32>, din : UInt<32>}
+    output dcache : {re : UInt<1>, flip dout : UInt<32>, we : UInt<4>, addr : UInt<32>, din : UInt<32>}
     input stall : UInt<1>
     
     inst alu of ALU
@@ -255,27 +235,29 @@ circuit Datapath :
     on-reset ew_inst := UInt<32>(0)
     reg ew_pc : UInt
     reg ew_alu : UInt
-    node T_573 = sub-wrap(UInt<14>(8192), UInt<14>(4))
-    reg pc : UInt<14>
-    on-reset pc := T_573
-    node T_574 = eq(ctrl.pc_sel, UInt<1>(1))
-    node T_575 = bit-or(T_574, brCond.taken)
-    node T_576 = add-wrap(pc, UInt<14>(4))
-    node iaddr = mux(T_575, alu.sum, Pad(T_576,32))
-    node T_577 = eq(ctrl.inst_type, UInt<1>(1))
-    node T_578 = bit-or(T_577, brCond.taken)
-    node inst = mux(T_578, UInt<32>(19), icache.dout)
+    node T_571 = sub-wrap(UInt<14>(8192), UInt<32>(4))
+    reg pc : UInt<32>
+    on-reset pc := T_571
+    node T_572 = eq(ctrl.pc_sel, UInt<1>(1))
+    node T_573 = bit-or(T_572, brCond.taken)
+    node T_574 = add-wrap(pc, UInt<3>(4))
+    node iaddr = mux(T_573, alu.sum, T_574)
+    node T_575 = eq(ctrl.inst_type, UInt<1>(1))
+    node T_576 = bit-or(T_575, brCond.taken)
+    node inst = mux(T_576, UInt<32>(19), icache.dout)
+    icache.we := UInt<1>(0)
+    icache.din := UInt<1>(0)
     icache.addr := iaddr
     icache.re := ctrl.inst_re
-    node T_579 = eq(dcache.we, UInt<4>(0))
-    node T_580 = bit-not(T_579)
-    node T_581 = bit-not(T_580)
-    node T_582 = bit-and(icache.re, T_581)
-    node T_583 = mux(T_582, iaddr, Pad(pc,32))
-    pc := T_583
-    node T_584 = bit-not(stall)
-    when T_584 : 
-      fe_pc := Pad(pc,?)
+    node T_577 = eq(dcache.we, UInt<1>(0))
+    node T_578 = bit-not(T_577)
+    node T_579 = bit-not(T_578)
+    node T_580 = bit-and(icache.re, T_579)
+    node T_581 = mux(T_580, iaddr, pc)
+    pc := T_581
+    node T_582 = bit-not(stall)
+    when T_582 : 
+      fe_pc := pc
       fe_inst := inst
     ctrl.inst := fe_inst
     ctrl.stall := stall
@@ -286,103 +268,98 @@ circuit Datapath :
     regFile.raddr2 := rs2_addr
     immGen.inst := fe_inst
     immGen.sel := ctrl.imm_sel
-    node T_585 = eq(rs1_addr, UInt<5>(0))
-    node rs1NotZero = bit-not(T_585)
-    node T_586 = eq(rs2_addr, UInt<5>(0))
-    node rs2NotZero = bit-not(T_586)
-    node T_587 = eq(ctrl.wb_sel, UInt<2>(0))
-    node alutype = bit-and(ctrl.wb_en, T_587)
+    node T_583 = eq(rs1_addr, UInt<1>(0))
+    node rs1NotZero = bit-not(T_583)
+    node T_584 = eq(rs2_addr, UInt<1>(0))
+    node rs2NotZero = bit-not(T_584)
+    node T_585 = eq(ctrl.wb_sel, UInt<2>(0))
+    node alutype = bit-and(ctrl.wb_en, T_585)
     node ex_rd_addr = bits(ew_inst, 11, 7)
-    node T_588 = bit-and(alutype, rs1NotZero)
-    node T_589 = eq(rs1_addr, ex_rd_addr)
-    node T_590 = bit-and(T_588, T_589)
-    node rs1 = mux(T_590, Pad(ew_alu,?), Pad(regFile.rdata1,?))
-    node T_591 = bit-and(alutype, rs2NotZero)
-    node T_592 = eq(rs2_addr, ex_rd_addr)
-    node T_593 = bit-and(T_591, T_592)
-    node rs2 = mux(T_593, Pad(ew_alu,?), Pad(regFile.rdata2,?))
-    node T_594 = eq(ctrl.A_sel, UInt<1>(0))
-    node T_595 = mux(T_594, Pad(rs1,?), Pad(fe_pc,?))
-    alu.A := Pad(T_595,?)
-    node T_596 = eq(ctrl.B_sel, UInt<1>(0))
-    node T_597 = mux(T_596, Pad(rs2,?), Pad(immGen.out,?))
-    alu.B := Pad(T_597,?)
+    node T_586 = bit-and(alutype, rs1NotZero)
+    node T_587 = eq(rs1_addr, ex_rd_addr)
+    node T_588 = bit-and(T_586, T_587)
+    node rs1 = mux(T_588, ew_alu, regFile.rdata1)
+    node T_589 = bit-and(alutype, rs2NotZero)
+    node T_590 = eq(rs2_addr, ex_rd_addr)
+    node T_591 = bit-and(T_589, T_590)
+    node rs2 = mux(T_591, ew_alu, regFile.rdata2)
+    node T_592 = eq(ctrl.A_sel, UInt<1>(0))
+    node T_593 = mux(T_592, rs1, fe_pc)
+    alu.A := T_593
+    node T_594 = eq(ctrl.B_sel, UInt<1>(0))
+    node T_595 = mux(T_594, rs2, immGen.out)
+    alu.B := T_595
     alu.alu_op := ctrl.alu_op
-    brCond.rs1 := Pad(rs1,?)
-    brCond.rs2 := Pad(rs2,?)
+    brCond.rs1 := rs1
+    brCond.rs2 := rs2
     brCond.br_type := ctrl.br_type
-    node T_598 = bit(alu.sum, 1)
-    node T_599 = dshl(T_598, UInt<3>(4))
-    node T_600 = bit(alu.sum, 0)
-    node T_601 = dshl(T_600, UInt<2>(3))
-    node woffset = bit-or(T_599, T_601)
+    node T_596 = bit(alu.sum, 1)
+    node T_597 = dshl(T_596, UInt<3>(4))
+    node T_598 = bit(alu.sum, 0)
+    node T_599 = dshl(T_598, UInt<2>(3))
+    node woffset = bit-or(T_597, T_599)
     dcache.re := ctrl.data_re
-    node T_602 = mux(stall, Pad(ew_alu,?), Pad(alu.sum,?))
-    dcache.addr := Pad(T_602,?)
-    node T_603 = bits(alu.sum, 1, 0)
-    node T_604 = dshl(UInt<2>(3), T_603)
-    node T_605 = bits(alu.sum, 1, 0)
-    node T_606 = dshl(UInt<1>(1), T_605)
+    node T_600 = mux(stall, ew_alu, alu.sum)
+    dcache.addr := T_600
+    node T_601 = bits(alu.sum, 1, 0)
+    node T_602 = dshl(UInt<2>(3), T_601)
+    node T_603 = bits(T_602, 3, 0)
+    node T_604 = bits(alu.sum, 1, 0)
+    node T_605 = dshl(UInt<1>(1), T_604)
+    node T_606 = bits(T_605, 3, 0)
     node T_607 = eq(UInt<2>(2), ctrl.st_type)
-    node T_608 = mux(T_607, T_606, UInt<5>(0))
+    node T_608 = mux(T_607, T_606, UInt<4>(0))
     node T_609 = eq(UInt<2>(1), ctrl.st_type)
-    node T_610 = mux(T_609, T_604, Pad(T_608,6))
+    node T_610 = mux(T_609, T_603, T_608)
     node T_611 = eq(UInt<2>(0), ctrl.st_type)
-    node T_612 = mux(T_611, UInt<6>(15), T_610)
-    node T_613 = mux(stall, UInt<6>(0), T_612)
+    node T_612 = mux(T_611, UInt<4>(15), T_610)
+    node T_613 = mux(stall, UInt<4>(0), T_612)
     dcache.we := T_613
     node T_614 = dshl(rs2, woffset)
-    dcache.din := Pad(T_614,?)
-    node T_615 = bit-not(stall)
-    when T_615 : 
-      ew_pc := Pad(fe_pc,?)
+    node T_615 = bits(T_614, 31, 0)
+    dcache.din := T_615
+    node T_616 = bit-not(stall)
+    when T_616 : 
+      ew_pc := fe_pc
       ew_inst := fe_inst
-      ew_alu := Pad(alu.out,?)
-    node T_616 = bit(ew_alu, 1)
-    node T_617 = dshl(T_616, UInt<3>(4))
-    node T_618 = bit(ew_alu, 0)
-    node T_619 = dshl(T_618, UInt<2>(3))
-    node loffset = bit-or(T_617, T_619)
+      ew_alu := alu.out
+    node T_617 = bit(ew_alu, 1)
+    node T_618 = dshl(T_617, UInt<3>(4))
+    node T_619 = bit(ew_alu, 0)
+    node T_620 = dshl(T_619, UInt<2>(3))
+    node loffset = bit-or(T_618, T_620)
     node lshift = dshr(dcache.dout, loffset)
-    node T_620 = bits(lshift, 15, 0)
-    wire T_621 : SInt<16>
-    T_621 := T_620
-    node T_622 = Pad(T_621, 32)
-    wire T_623 : UInt<32>
-    T_623 := T_622
-    node T_624 = bits(lshift, 7, 0)
-    wire T_625 : SInt<8>
-    T_625 := T_624
-    node T_626 = Pad(T_625, 32)
-    wire T_627 : UInt<32>
-    T_627 := T_626
-    node T_628 = bits(lshift, 15, 0)
-    wire T_629 : UInt<16>
-    T_629 := T_628
+    node T_621 = bits(lshift, 15, 0)
+    node T_622 = convert(T_621)
+    node T_623 = pad(T_622, 32)
+    node T_624 = as-UInt(T_623)
+    node T_625 = bits(lshift, 7, 0)
+    node T_626 = convert(T_625)
+    node T_627 = pad(T_626, 32)
+    node T_628 = as-UInt(T_627)
+    node T_629 = bits(lshift, 15, 0)
     node T_630 = bits(lshift, 7, 0)
-    wire T_631 : UInt<8>
-    T_631 := T_630
-    node T_632 = eq(UInt<3>(4), ctrl.ld_type)
-    node T_633 = mux(T_632, Pad(T_631,32), dcache.dout)
-    node T_634 = eq(UInt<3>(3), ctrl.ld_type)
-    node T_635 = mux(T_634, Pad(T_629,32), T_633)
-    node T_636 = eq(UInt<3>(2), ctrl.ld_type)
-    node T_637 = mux(T_636, T_627, T_635)
-    node T_638 = eq(UInt<3>(1), ctrl.ld_type)
-    node load = mux(T_638, T_623, T_637)
+    node T_631 = eq(UInt<3>(4), ctrl.ld_type)
+    node T_632 = mux(T_631, T_630, dcache.dout)
+    node T_633 = eq(UInt<3>(3), ctrl.ld_type)
+    node T_634 = mux(T_633, T_629, T_632)
+    node T_635 = eq(UInt<3>(2), ctrl.ld_type)
+    node T_636 = mux(T_635, T_628, T_634)
+    node T_637 = eq(UInt<3>(1), ctrl.ld_type)
+    node load = mux(T_637, T_624, T_636)
     inst csr of CSR
     host := csr.host
-    csr.src := Pad(ew_alu,?)
-    node T_639 = bits(ew_inst, 31, 20)
-    csr.addr := T_639
+    csr.src := ew_alu
+    node T_638 = bits(ew_inst, 31, 20)
+    csr.addr := T_638
     csr.cmd := ctrl.csr_cmd
-    node T_640 = add-wrap(Pad(ew_pc,?), Pad(UInt<3>(4),?))
-    node T_641 = eq(UInt<2>(3), ctrl.wb_sel)
-    node T_642 = mux(T_641, Pad(csr.data,?), Pad(ew_alu,?))
-    node T_643 = eq(UInt<2>(2), ctrl.wb_sel)
-    node T_644 = mux(T_643, Pad(T_640,?), Pad(T_642,?))
-    node T_645 = eq(UInt<2>(1), ctrl.wb_sel)
-    node regWrite = mux(T_645, Pad(load,?), Pad(T_644,?))
+    node T_639 = add-wrap(ew_pc, UInt<3>(4))
+    node T_640 = eq(UInt<2>(3), ctrl.wb_sel)
+    node T_641 = mux(T_640, csr.data, ew_alu)
+    node T_642 = eq(UInt<2>(2), ctrl.wb_sel)
+    node T_643 = mux(T_642, T_639, T_641)
+    node T_644 = eq(UInt<2>(1), ctrl.wb_sel)
+    node regWrite = mux(T_644, load, T_643)
     regFile.wen := ctrl.wb_en
     regFile.waddr := ex_rd_addr
-    regFile.wdata := Pad(regWrite,?)
+    regFile.wdata := regWrite
diff --git a/test/chisel3/LFSR16.fir b/test/chisel3/LFSR16.fir
index b635e4bf..cdf1b835 100644
--- a/test/chisel3/LFSR16.fir
+++ b/test/chisel3/LFSR16.fir
@@ -1,24 +1,22 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
-; CHECK: Done!
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
 
 circuit LFSR16 : 
   module LFSR16 : 
     output out : UInt<16>
     input inc : UInt<1>
     
-    node T_16 = UInt<16>(1)
     reg res : UInt<16>
-    on-reset res := T_16
+    on-reset res := UInt<16>(1)
     when inc : 
-      node T_17 = bit(res, 0)
-      node T_18 = bit(res, 2)
-      node T_19 = bit-xor(T_17, T_18)
-      node T_20 = bit(res, 3)
-      node T_21 = bit-xor(T_19, T_20)
-      node T_22 = bit(res, 5)
-      node T_23 = bit-xor(T_21, T_22)
-      node T_24 = bits(res, 15, 1)
-      node T_25 = cat(T_23, T_24)
-      res := T_25
+      node T_16 = bit(res, 0)
+      node T_17 = bit(res, 2)
+      node T_18 = bit-xor(T_16, T_17)
+      node T_19 = bit(res, 3)
+      node T_20 = bit-xor(T_18, T_19)
+      node T_21 = bit(res, 5)
+      node T_22 = bit-xor(T_20, T_21)
+      node T_23 = bits(res, 15, 1)
+      node T_24 = cat(T_22, T_23)
+      res := T_24
     out := res
-
diff --git a/test/chisel3/Memory.fir b/test/chisel3/Memory.fir
deleted file mode 100644
index 67f0a7cf..00000000
--- a/test/chisel3/Memory.fir
+++ /dev/null
@@ -1,204 +0,0 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
-; CHECK: Done!
-
-circuit Memory : 
-  module Queue : 
-    output count : UInt<3>
-    input enq : {valid : UInt<1>, flip ready : UInt<1>, bits : {mask : UInt<4>, rw : UInt<1>, tag : UInt<5>, addr : UInt<32>}}
-    output deq : {valid : UInt<1>, flip ready : UInt<1>, bits : {mask : UInt<4>, rw : UInt<1>, tag : UInt<5>, addr : UInt<32>}}
-    
-    mem ram : {mask : UInt<4>, rw : UInt<1>, tag : UInt<5>, addr : UInt<32>}[4]
-    reg T_292 : UInt<2>
-    on-reset T_292 := UInt<2>(0)
-    reg T_293 : UInt<2>
-    on-reset T_293 := UInt<2>(0)
-    reg maybe_full : UInt<1>
-    on-reset maybe_full := UInt<1>(0)
-    node ptr_match = eq(T_292, T_293)
-    node T_294 = bit-not(maybe_full)
-    node empty = bit-and(ptr_match, T_294)
-    node full = bit-and(ptr_match, maybe_full)
-    node maybe_flow = bit-and(UInt<1>(0), empty)
-    node do_flow = bit-and(maybe_flow, deq.ready)
-    node T_295 = bit-and(enq.ready, enq.valid)
-    node T_296 = bit-not(do_flow)
-    node do_enq = bit-and(T_295, T_296)
-    node T_297 = bit-and(deq.ready, deq.valid)
-    node T_298 = bit-not(do_flow)
-    node do_deq = bit-and(T_297, T_298)
-    when do_enq : 
-      accessor T_299 = ram[T_292]
-      T_299 := enq.bits
-      node T_300 = eq(T_292, UInt<2>(3))
-      node T_301 = bit-and(UInt<1>(0), T_300)
-      node T_302 = add-wrap(T_292, UInt<2>(1))
-      node T_303 = mux(T_301, UInt<2>(0), T_302)
-      T_292 := T_303
-    when do_deq : 
-      node T_304 = eq(T_293, UInt<2>(3))
-      node T_305 = bit-and(UInt<1>(0), T_304)
-      node T_306 = add-wrap(T_293, UInt<2>(1))
-      node T_307 = mux(T_305, UInt<2>(0), T_306)
-      T_293 := T_307
-    node T_308 = neq(do_enq, do_deq)
-    when T_308 : maybe_full := do_enq
-    node T_309 = bit-not(empty)
-    node T_310 = bit-and(UInt<1>(0), enq.valid)
-    node T_311 = bit-or(T_309, T_310)
-    deq.valid := T_311
-    node T_312 = bit-not(full)
-    node T_313 = bit-and(UInt<1>(0), deq.ready)
-    node T_314 = bit-or(T_312, T_313)
-    enq.ready := T_314
-    accessor T_315 = ram[T_293]
-    wire T_316 : {mask : UInt<4>, rw : UInt<1>, tag : UInt<5>, addr : UInt<32>}
-    node T_317 = mux(maybe_flow, enq.bits.mask, T_315.mask)
-    T_316.mask := T_317
-    node T_318 = mux(maybe_flow, enq.bits.rw, T_315.rw)
-    T_316.rw := T_318
-    node T_319 = mux(maybe_flow, enq.bits.tag, T_315.tag)
-    T_316.tag := T_319
-    node T_320 = mux(maybe_flow, enq.bits.addr, T_315.addr)
-    T_316.addr := T_320
-    deq.bits := T_316
-    node ptr_diff = sub-wrap(T_292, T_293)
-    node T_321 = bit-and(maybe_full, ptr_match)
-    node T_322 = cat(T_321, ptr_diff)
-    count := Pad(T_322,3)
-  module Queue_228 : 
-    output count : UInt<3>
-    input enq : {valid : UInt<1>, flip ready : UInt<1>, bits : {data : UInt<32>}}
-    output deq : {valid : UInt<1>, flip ready : UInt<1>, bits : {data : UInt<32>}}
-    
-    mem ram : {data : UInt<32>}[4]
-    reg T_323 : UInt<2>
-    on-reset T_323 := UInt<2>(0)
-    reg T_324 : UInt<2>
-    on-reset T_324 := UInt<2>(0)
-    reg maybe_full : UInt<1>
-    on-reset maybe_full := UInt<1>(0)
-    node ptr_match = eq(T_323, T_324)
-    node T_325 = bit-not(maybe_full)
-    node empty = bit-and(ptr_match, T_325)
-    node full = bit-and(ptr_match, maybe_full)
-    node maybe_flow = bit-and(UInt<1>(0), empty)
-    node do_flow = bit-and(maybe_flow, deq.ready)
-    node T_326 = bit-and(enq.ready, enq.valid)
-    node T_327 = bit-not(do_flow)
-    node do_enq = bit-and(T_326, T_327)
-    node T_328 = bit-and(deq.ready, deq.valid)
-    node T_329 = bit-not(do_flow)
-    node do_deq = bit-and(T_328, T_329)
-    when do_enq : 
-      accessor T_330 = ram[T_323]
-      T_330 := enq.bits
-      node T_331 = eq(T_323, UInt<2>(3))
-      node T_332 = bit-and(UInt<1>(0), T_331)
-      node T_333 = add-wrap(T_323, UInt<2>(1))
-      node T_334 = mux(T_332, UInt<2>(0), T_333)
-      T_323 := T_334
-    when do_deq : 
-      node T_335 = eq(T_324, UInt<2>(3))
-      node T_336 = bit-and(UInt<1>(0), T_335)
-      node T_337 = add-wrap(T_324, UInt<2>(1))
-      node T_338 = mux(T_336, UInt<2>(0), T_337)
-      T_324 := T_338
-    node T_339 = neq(do_enq, do_deq)
-    when T_339 : maybe_full := do_enq
-    node T_340 = bit-not(empty)
-    node T_341 = bit-and(UInt<1>(0), enq.valid)
-    node T_342 = bit-or(T_340, T_341)
-    deq.valid := T_342
-    node T_343 = bit-not(full)
-    node T_344 = bit-and(UInt<1>(0), deq.ready)
-    node T_345 = bit-or(T_343, T_344)
-    enq.ready := T_345
-    accessor T_346 = ram[T_324]
-    wire T_347 : {data : UInt<32>}
-    node T_348 = mux(maybe_flow, enq.bits.data, T_346.data)
-    T_347.data := T_348
-    deq.bits := T_347
-    node ptr_diff = sub-wrap(T_323, T_324)
-    node T_349 = bit-and(maybe_full, ptr_match)
-    node T_350 = cat(T_349, ptr_diff)
-    count := Pad(T_350,3)
-  module Memory : 
-    output stall : UInt<1>
-    output memory : {flip resp : {valid : UInt<1>, flip ready : UInt<1>, bits : {data : UInt<32>, tag : UInt<5>}}, req_data : {valid : UInt<1>, flip ready : UInt<1>, bits : {data : UInt<32>}}, req_cmd : {valid : UInt<1>, flip ready : UInt<1>, bits : {mask : UInt<4>, rw : UInt<1>, tag : UInt<5>, addr : UInt<32>}}}
-    input icache : {re : UInt<1>, addr : UInt<32>, din : UInt<32>, flip dout : UInt<32>, we : UInt<4>}
-    input dcache : {re : UInt<1>, addr : UInt<32>, din : UInt<32>, flip dout : UInt<32>, we : UInt<4>}
-    
-    inst memReqCmdQueue of Queue
-    inst memReqDataQueue of Queue_228
-    reg state : UInt<1>
-    on-reset state := UInt<1>(0)
-    reg tag : UInt<5>
-    on-reset tag := UInt<5>(0)
-    node T_351 = eq(state, UInt<1>(0))
-    node T_352 = bit-or(icache.re, dcache.re)
-    node T_353 = eq(dcache.we, UInt<4>(0))
-    node T_354 = bit-not(T_353)
-    node T_355 = bit-or(T_352, T_354)
-    node cpuReq = bit-and(T_351, T_355)
-    node T_356 = bits(icache.addr, 31, 2)
-    node iaddr = cat(T_356, UInt<2>(0))
-    node T_357 = bits(dcache.addr, 31, 2)
-    node daddr = cat(T_357, UInt<2>(0))
-    reg idata : UInt
-    reg ddata : UInt
-    reg ire : UInt<1>
-    reg dre : UInt<1>
-    icache.dout := Pad(idata,?)
-    dcache.dout := Pad(ddata,?)
-    memReqCmdQueue.deq := memory.req_cmd
-    memReqDataQueue.deq := memory.req_data
-    memory.resp.ready := UInt<1>(0)
-    node T_358 = eq(state, UInt<1>(1))
-    node T_359 = bit-not(memReqCmdQueue.enq.ready)
-    node T_360 = bit-or(T_358, T_359)
-    node T_361 = bit-not(memReqDataQueue.enq.ready)
-    node T_362 = bit-or(T_360, T_361)
-    stall := T_362
-    node T_363 = eq(dcache.we, UInt<4>(0))
-    node T_364 = bit-not(T_363)
-    memReqCmdQueue.enq.bits.rw := T_364
-    memReqCmdQueue.enq.bits.tag := tag
-    node T_365 = eq(dcache.we, UInt<4>(0))
-    node T_366 = bit-not(T_365)
-    node T_367 = bit-not(icache.re)
-    node T_368 = bit-or(T_366, T_367)
-    node T_369 = mux(T_368, daddr, iaddr)
-    memReqCmdQueue.enq.bits.addr := T_369
-    memReqCmdQueue.enq.bits.mask := dcache.we
-    node T_370 = bit-and(memReqDataQueue.enq.ready, cpuReq)
-    memReqCmdQueue.enq.valid := T_370
-    memReqDataQueue.enq.bits.data := dcache.din
-    node T_371 = bit-and(memReqCmdQueue.enq.ready, cpuReq)
-    node T_372 = eq(dcache.we, UInt<4>(0))
-    node T_373 = bit-not(T_372)
-    node T_374 = bit-and(T_371, T_373)
-    memReqDataQueue.enq.valid := T_374
-    node T_375 = eq(UInt<1>(0), state)
-    when T_375 : 
-      node T_376 = bit-or(icache.re, dcache.re)
-      node T_377 = eq(dcache.we, UInt<4>(0))
-      node T_378 = bit-not(T_377)
-      node T_379 = bit-not(T_378)
-      node T_380 = bit-and(T_376, T_379)
-      node T_381 = bit-and(T_380, memReqCmdQueue.enq.ready)
-      when T_381 : 
-        ire := icache.re
-        dre := dcache.re
-        state := UInt<1>(1)
-    node T_382 = eq(UInt<1>(1), state)
-    when T_382 : 
-      memory.resp.ready := UInt<1>(1)
-      node T_383 = eq(memory.resp.bits.tag, tag)
-      node T_384 = bit-and(memory.resp.valid, T_383)
-      when T_384 : 
-        state := UInt<1>(0)
-        node T_385 = add-wrap(tag, UInt<5>(1))
-        tag := T_385
-        memory.resp.ready := UInt<1>(0)
-        when ire : idata := Pad(memory.resp.bits.data,?)
-        when dre : ddata := Pad(memory.resp.bits.data,?)
diff --git a/test/chisel3/MemorySearch.fir b/test/chisel3/MemorySearch.fir
index e62f35ba..375bfcff 100644
--- a/test/chisel3/MemorySearch.fir
+++ b/test/chisel3/MemorySearch.fir
@@ -1,45 +1,34 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
-; CHECK: Done!
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
 circuit MemorySearch : 
   module MemorySearch : 
     input target : UInt<4>
     output address : UInt<3>
     input en : UInt<1>
-    output odone : UInt<1>
+    output done : UInt<1>
     
-    node T_35 = UInt<3>(0)
     reg index : UInt<3>
-    on-reset index := T_35
-    node T_36 = UInt<1>(0)
-    node T_37 = UInt<3>(4)
-    node T_38 = UInt<4>(15)
-    node T_39 = UInt<4>(14)
-    node T_40 = UInt<2>(2)
-    node T_41 = UInt<3>(5)
-    node T_42 = UInt<4>(13)
-    wire elts : UInt<1>[7]
-    elts[0] := T_36
-    elts[1] := T_37
-    elts[2] := T_38
-    elts[3] := T_39
-    elts[4] := T_40
-    elts[5] := T_41
-    elts[6] := T_42
+    on-reset index := UInt<3>(0)
+    wire elts : UInt<4>[7]
+    elts[0] := UInt<4>(0)
+    elts[1] := UInt<4>(4)
+    elts[2] := UInt<4>(15)
+    elts[3] := UInt<4>(14)
+    elts[4] := UInt<4>(2)
+    elts[5] := UInt<4>(5)
+    elts[6] := UInt<4>(13)
     accessor elt = elts[index]
-    node T_43 = bit-not(en)
-    node T_44 = eq(elt, target)
-    node T_45 = UInt<3>(7)
-    node T_46 = eq(index, T_45)
-    node T_47 = bit-or(T_44, T_46)
-    node done = bit-and(T_43, T_47)
-    when en : 
-      node T_48 = UInt<1>(0)
-      index := T_48
+    node T_35 = bit-not(en)
+    node T_36 = eq(elt, target)
+    node T_37 = eq(index, UInt<3>(7))
+    node T_38 = bit-or(T_36, T_37)
+    node end = bit-and(T_35, T_38)
+    when en : index := UInt<1>(0)
     else : 
-      node T_49 = bit-not(done)
-      when T_49 : 
-        node T_50 = UInt<1>(1)
-        node T_51 = add(index, T_50)
-        index := T_51
-    odone := done
+      node T_39 = bit-not(end)
+      when T_39 : 
+        node T_40 = add-wrap(index, UInt<1>(1))
+        index := T_40
+    done := end
     address := index
diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir
index a53c9549..87d0fed0 100644
--- a/test/chisel3/ModuleVec.fir
+++ b/test/chisel3/ModuleVec.fir
@@ -1,30 +1,29 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
-; CHECK: Done!
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
 circuit ModuleVec : 
   module PlusOne : 
     input in : UInt<32>
     output out : UInt<32>
     
-    node T_33 = UInt<1>(1)
-    node T_34 = add-wrap(Pad(in,?), Pad(T_33,?))
-    out := Pad(T_34,?)
+    node T_33 = add-wrap(in, UInt<1>(1))
+    out := T_33
   module PlusOne_25 : 
     input in : UInt<32>
     output out : UInt<32>
     
-    node T_35 = UInt<1>(1)
-    node T_36 = add-wrap(Pad(in,?), Pad(T_35,?))
-    out := Pad(T_36,?)
+    node T_34 = add-wrap(in, UInt<1>(1))
+    out := T_34
   module ModuleVec : 
     input ins : UInt<32>[2]
     output outs : UInt<32>[2]
     
-    inst T_37 of PlusOne
-    inst T_38 of PlusOne_25
-    wire pluses : { flip in : UInt<32>, out : UInt<32>}[2]
-    pluses[0] := T_37
-    pluses[1] := T_38
-    pluses[0].in := Pad(ins[0],?)
-    outs[0] := Pad(pluses[0].out,?)
-    pluses[1].in := Pad(ins[1],?)
-    outs[1] := Pad(pluses[1].out,?)
+    inst T_35 of PlusOne
+    inst T_36 of PlusOne_25
+    wire pluses : {flip in : UInt<32>, out : UInt<32>}[2]
+    pluses[0] := T_35
+    pluses[1] := T_36
+    pluses[0].in := ins[0]
+    outs[0] := pluses[0].out
+    pluses[1].in := ins[1]
+    outs[1] := pluses[1].out
diff --git a/test/chisel3/Mul.fir b/test/chisel3/Mul.fir
index 46a8c9b9..fab610b6 100644
--- a/test/chisel3/Mul.fir
+++ b/test/chisel3/Mul.fir
@@ -1,10 +1,11 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
-; CHECK: Done!
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
 circuit Mul : 
   module Mul : 
     input x : UInt<2>
-    input y : UInt<2>
     output z : UInt<4>
+    input y : UInt<2>
     
     wire tbl : UInt<4>[16]
     tbl[0] := UInt<4>(0)
@@ -24,6 +25,6 @@ circuit Mul :
     tbl[14] := UInt<4>(6)
     tbl[15] := UInt<4>(9)
     node T_42 = shl(x, 2)
-    node T_43 = bit-or(Pad(T_42,?), Pad(y,?))
+    node T_43 = bit-or(T_42, y)
     accessor T_44 = tbl[T_43]
-    z := Pad(T_44,?)
+    z := T_44
diff --git a/test/chisel3/Outer.fir b/test/chisel3/Outer.fir
index 2e1e4475..a7631277 100644
--- a/test/chisel3/Outer.fir
+++ b/test/chisel3/Outer.fir
@@ -1,12 +1,12 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
-; CHECK: Done!
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
 circuit Outer : 
   module Inner : 
     input in : UInt<8>
     output out : UInt<8>
     
-    node T_14 = UInt<1>(1)
-    node T_15 = add(in, T_14)
+    node T_15 = add-wrap(in, UInt<1>(1))
     out := T_15
   module Outer : 
     input in : UInt<8>
@@ -14,6 +14,6 @@ circuit Outer :
     
     inst T_16 of Inner
     T_16.in := in
-    node T_17 = UInt<2>(2)
-    node T_18 = mul(T_16.out, T_17)
+    node T_17 = mul(T_16.out, UInt<2>(2))
+    node T_18 = bits(T_17, 7, 0)
     out := T_18
diff --git a/test/chisel3/RegisterVecShift.fir b/test/chisel3/RegisterVecShift.fir
index 5a184366..3a9658eb 100644
--- a/test/chisel3/RegisterVecShift.fir
+++ b/test/chisel3/RegisterVecShift.fir
@@ -1,5 +1,6 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
-; CHECK: Done!
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
 circuit RegisterVecShift : 
   module RegisterVecShift : 
     input load : UInt<1>
@@ -9,26 +10,18 @@ circuit RegisterVecShift :
     
     reg delays : UInt<4>[4]
     when reset : 
-      node T_39 = UInt<4>(0)
-      node T_40 = UInt<4>(0)
-      node T_41 = UInt<4>(0)
-      node T_42 = UInt<4>(0)
-      wire T_43 : UInt<4>[4]
-      T_43[0] := T_39
-      T_43[1] := T_40
-      T_43[2] := T_41
-      T_43[3] := T_42
-      delays := T_43
-    node T_44 = UInt<3>(5)
-    node T_45 = bit-and(T_44, load)
-    node T_46 = UInt<3>(4)
-    node T_47 = eq(T_45, T_46)
-    when T_47 : 
+      wire T_33 : UInt<4>[4]
+      T_33[0] := UInt<4>(0)
+      T_33[1] := UInt<4>(0)
+      T_33[2] := UInt<4>(0)
+      T_33[3] := UInt<4>(0)
+      delays := T_33
+    when load : 
       delays[0] := ins[0]
       delays[1] := ins[1]
       delays[2] := ins[2]
       delays[3] := ins[3]
-     else : when shift : 
+    else : when shift : 
         delays[0] := ins[0]
         delays[1] := delays[0]
         delays[2] := delays[1]
diff --git a/test/chisel3/SIntOps.fir b/test/chisel3/SIntOps.fir
index f79d0fca..ee1aa366 100644
--- a/test/chisel3/SIntOps.fir
+++ b/test/chisel3/SIntOps.fir
@@ -1,5 +1,5 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
-; CHECK: Done!
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
 
 circuit SIntOps : 
   module SIntOps : 
@@ -20,41 +20,34 @@ circuit SIntOps :
     output greateqout : UInt<1>
     output negout : SInt<16>
     
-    wire ub : UInt
-    ub := b
-    node T_44 = add-wrap(Pad(a,?), Pad(b,?))
-    addout := Pad(T_44,?)
-    node T_45 = sub-wrap(Pad(a,?), Pad(b,?))
-    subout := Pad(T_45,?)
-    node T_46 = mul(Pad(a,?), Pad(b,?))
-    node T_47 = bits(T_46, 15, 0)
-    timesout := Pad(T_47,?)
-    node T_48 = eq(Pad(b,?), Pad(SInt<1>(0),?))
-    node T_49 = mux(Pad(T_48,?), Pad(SInt<2>(1),?), Pad(b,?))
-    node T_50 = div(Pad(a,?), Pad(T_49,?))
-    divout := Pad(T_50,?)
-    modout := Pad(UInt<1>(0),?)
-    node T_51 = bits(ub, 3, 0)
-    node T_52 = dshl(a, T_51)
-    node T_53 = bits(T_52, 15, 0)
-    wire T_54 : SInt
-    T_54 := T_53
-    lshiftout := Pad(T_54,?)
-    node T_55 = dshr(a, ub)
-    wire T_56 : SInt
-    T_56 := T_55
-    rshiftout := Pad(T_56,?)
-    node T_57 = lt(Pad(a,?), Pad(b,?))
-    lessout := Pad(T_57,?)
-    node T_58 = gt(Pad(a,?), Pad(b,?))
-    greatout := Pad(T_58,?)
-    node T_59 = eq(Pad(a,?), Pad(b,?))
-    eqout := Pad(T_59,?)
-    node T_60 = neq(Pad(a,?), Pad(b,?))
-    noteqout := Pad(T_60,?)
-    node T_61 = leq(Pad(a,?), Pad(b,?))
-    lesseqout := Pad(T_61,?)
-    node T_62 = geq(Pad(a,?), Pad(b,?))
-    greateqout := Pad(T_62,?)
-    node T_63 = sub-wrap(Pad(SInt<1>(0),?), Pad(a,?))
-    negout := Pad(T_63,?)
+    node ub = as-UInt(b)
+    node T_38 = add-wrap(a, b)
+    addout := T_38
+    node T_39 = sub-wrap(a, b)
+    subout := T_39
+    node T_40 = mul(a, b)
+    node T_41 = bits(T_40, 15, 0)
+    timesout := T_41
+    node T_42 = mul(a, b)
+    node T_43 = bits(T_42, 15, 0)
+    divout := T_43
+    modout := UInt<1>(0)
+    node T_44 = shl(a, 12)
+    node T_45 = bits(T_44, 15, 0)
+    lshiftout := T_45
+    node T_46 = shr(a, 8)
+    rshiftout := T_46
+    node T_47 = lt(a, b)
+    lessout := T_47
+    node T_48 = gt(a, b)
+    greatout := T_48
+    node T_49 = eq(a, b)
+    eqout := T_49
+    node T_50 = neq(a, b)
+    noteqout := T_50
+    node T_51 = leq(a, b)
+    lesseqout := T_51
+    node T_52 = geq(a, b)
+    greateqout := T_52
+    node T_53 = sub-wrap(SInt<1>(0), a)
+    negout := T_53
diff --git a/test/chisel3/Stack.fir b/test/chisel3/Stack.fir
index a6f33189..84cb6ccd 100644
--- a/test/chisel3/Stack.fir
+++ b/test/chisel3/Stack.fir
@@ -1,5 +1,6 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
-; CHECK: Done!
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
 circuit Stack : 
   module Stack : 
     input push : UInt<1>
@@ -9,35 +10,27 @@ circuit Stack :
     input dataIn : UInt<32>
     
     mem stack_mem : UInt<32>[16]
-    node T_30 = UInt<5>(0)
     reg sp : UInt<5>
-    on-reset sp := T_30
-    node T_31 = UInt<32>(0)
+    on-reset sp := UInt<5>(0)
     reg out : UInt<32>
-    on-reset out := T_31
+    on-reset out := UInt<32>(0)
     when en : 
-      node T_32 = UInt<5>(16)
-      node T_33 = lt(sp, T_32)
-      node T_34 = bit-and(push, T_33)
-      when T_34 : 
-        accessor T_35 = stack_mem[sp]
-        T_35 := dataIn
-        node T_36 = UInt<1>(1)
-        node T_37 = add-wrap(sp, T_36)
-        sp := T_37
+      node T_30 = lt(sp, UInt<5>(16))
+      node T_31 = bit-and(push, T_30)
+      when T_31 : 
+        accessor T_32 = stack_mem[sp]
+        T_32 := dataIn
+        node T_33 = add-wrap(sp, UInt<1>(1))
+        sp := T_33
       else : 
-        node T_38 = UInt<1>(0)
-        node T_39 = gt(sp, T_38)
-        node T_40 = bit-and(pop, T_39)
-        when T_40 : 
-          node T_41 = UInt<1>(1)
-          node T_42 = sub-wrap(sp, T_41)
-          sp := T_42
-      node T_43 = UInt<1>(0)
-      node T_44 = gt(sp, T_43)
-      when T_44 : 
-        node T_45 = UInt<1>(1)
-        node T_46 = sub-wrap(sp, T_45)
-        accessor T_47 = stack_mem[T_46]
-        out := T_47
+        node T_34 = gt(sp, UInt<1>(0))
+        node T_35 = bit-and(pop, T_34)
+        when T_35 : 
+          node T_36 = sub-wrap(sp, UInt<1>(1))
+          sp := T_36
+      node T_37 = gt(sp, UInt<1>(0))
+      when T_37 : 
+        node T_38 = sub-wrap(sp, UInt<1>(1))
+        accessor T_39 = stack_mem[T_38]
+        out := T_39
     dataOut := out