diff options
Diffstat (limited to 'test/chisel3/ModuleVec.fir')
| -rw-r--r-- | test/chisel3/ModuleVec.fir | 33 |
1 files changed, 16 insertions, 17 deletions
diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir index a53c9549..87d0fed0 100644 --- a/test/chisel3/ModuleVec.fir +++ b/test/chisel3/ModuleVec.fir @@ -1,30 +1,29 @@ -; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s -; CHECK: Done! +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +;CHECK: Done! + circuit ModuleVec : module PlusOne : input in : UInt<32> output out : UInt<32> - node T_33 = UInt<1>(1) - node T_34 = add-wrap(Pad(in,?), Pad(T_33,?)) - out := Pad(T_34,?) + node T_33 = add-wrap(in, UInt<1>(1)) + out := T_33 module PlusOne_25 : input in : UInt<32> output out : UInt<32> - node T_35 = UInt<1>(1) - node T_36 = add-wrap(Pad(in,?), Pad(T_35,?)) - out := Pad(T_36,?) + node T_34 = add-wrap(in, UInt<1>(1)) + out := T_34 module ModuleVec : input ins : UInt<32>[2] output outs : UInt<32>[2] - inst T_37 of PlusOne - inst T_38 of PlusOne_25 - wire pluses : { flip in : UInt<32>, out : UInt<32>}[2] - pluses[0] := T_37 - pluses[1] := T_38 - pluses[0].in := Pad(ins[0],?) - outs[0] := Pad(pluses[0].out,?) - pluses[1].in := Pad(ins[1],?) - outs[1] := Pad(pluses[1].out,?) + inst T_35 of PlusOne + inst T_36 of PlusOne_25 + wire pluses : {flip in : UInt<32>, out : UInt<32>}[2] + pluses[0] := T_35 + pluses[1] := T_36 + pluses[0].in := ins[0] + outs[0] := pluses[0].out + pluses[1].in := ins[1] + outs[1] := pluses[1].out |