Added sequential memories. mem no longer exists, must declare either cmem or smem. Added firrtl-gensym utility to generate a hashmap of names

11 files changed, 50 insertions, 26 deletions

diff --git a/test/errors/high-form/Flip-Mem.fir b/test/errors/high-form/Flip-Mem.fir
index 662fc6f1..5725aa90 100644
--- a/test/errors/high-form/Flip-Mem.fir
+++ b/test/errors/high-form/Flip-Mem.fir
@@ -1,6 +1,8 @@
 ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
-; CHECK: Memory m cannot be a bundle type with flips.
+; CHECK: Memory m-c cannot be a bundle type with flips.
+; CHECK: Memory m-s cannot be a bundle type with flips.
 
 circuit Flip-Mem : 
   module Flip-Mem : 
-    mem m : {x : UInt<3>, flip y : UInt<5>}[10]
+    cmem m-c : {x : UInt<3>, flip y : UInt<5>}[10]
+    smem m-s : {x : UInt<3>, flip y : UInt<5>}[10]
diff --git a/test/features/BulkConnect.fir b/test/features/BulkConnect.fir
index eab0e602..f78ba45b 100644
--- a/test/features/BulkConnect.fir
+++ b/test/features/BulkConnect.fir
@@ -5,24 +5,24 @@ circuit Top :
     wire a : { w : UInt<42>, x : UInt<10>, flip y : UInt<42>, z : SInt<42>}
     wire b : { w : UInt<42>, x : UInt<20>, y : UInt<42>, z : UInt<42>}
     a <> b 
-    ; CHECK:     a_w := b_w
-    ; CHECK:     a_x := b_x
-    ; CHECK-NOT: a_y := b_y
-    ; CHECK-NOT: b_y := a_y
-    ; CHECK-NOT: a_z := b_z
+    ; CHECK:     a$w := b$w
+    ; CHECK:     a$x := b$x
+    ; CHECK-NOT: a$y := b$y
+    ; CHECK-NOT: b$y := a$y
+    ; CHECK-NOT: a$z := b$z
     
 
     wire c : { x : { y : UInt<1>, z : UInt<1>}}[4]
     wire d : { x : { y : UInt<1>}}[2]
     c <> d
-    ; CHECK:     c_0_x_y := d_0_x_y
-    ; CHECK:     c_1_x_y := d_1_x_y
-    ; CHECK-NOT: c_2_x_y := d_2_x_y
-    ; CHECK-NOT: c_3_x_y := d_3_x_y
-    ; CHECK-NOT: c_0_x_z := d_0_x_z
-    ; CHECK-NOT: c_1_x_z := d_1_x_z
-    ; CHECK-NOT: c_2_x_z := d_2_x_z
-    ; CHECK-NOT: c_3_x_z := d_3_x_z
+    ; CHECK:     c$0$x$y := d$0$x$y
+    ; CHECK:     c$1$x$y := d$1$x$y
+    ; CHECK-NOT: c$2$x$y := d$2$x$y
+    ; CHECK-NOT: c$3$x$y := d$3$x$y
+    ; CHECK-NOT: c$0$x$z := d$0$x$z
+    ; CHECK-NOT: c$1$x$z := d$1$x$z
+    ; CHECK-NOT: c$2$x$z := d$2$x$z
+    ; CHECK-NOT: c$3$x$z := d$3$x$z
 
 ;CHECK: Finished Lower To Ground
 ;CHECK: Done!
diff --git a/test/features/SeqMem.fir b/test/features/SeqMem.fir
new file mode 100644
index 00000000..998df8c9
--- /dev/null
+++ b/test/features/SeqMem.fir
@@ -0,0 +1,22 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+circuit Top : 
+  module Top : 
+    wire i : UInt<5>
+    wire i0 : UInt<5>
+    wire j : UInt<128>
+
+    i0 := UInt(10)
+
+    cmem m-com : UInt<128>[32]
+    accessor r-com = m-com[i]
+    accessor w-com = m-com[i]
+    j := r-com
+    w-com := j
+
+
+    smem m-seq : UInt<128>[32]
+    accessor r-seq = m-seq[i]
+    accessor w-seq = m-seq[i]
+    j := r-seq
+    w-seq := j
diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir
index cbde1486..eb396bcf 100644
--- a/test/passes/expand-accessors/accessor-mem.fir
+++ b/test/passes/expand-accessors/accessor-mem.fir
@@ -3,7 +3,7 @@
 ;CHECK: Expand Accessors
 circuit top :
    module top :
-      mem m : UInt<32>[2][2][2]
+      cmem m : UInt<32>[2][2][2]
       wire i : UInt<4>
       i := UInt(1)
       accessor a = m[i] ;CHECK: accessor a = m[i]
diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir
index 718f1d4b..114e5b5b 100644
--- a/test/passes/expand-whens/one-when.fir
+++ b/test/passes/expand-whens/one-when.fir
@@ -3,7 +3,7 @@
 ; CHECK: Expand Whens
 circuit top :
    module top :
-      mem m : UInt<1>[2]
+      cmem m : UInt<1>[2]
       wire i : UInt<1>
       wire p : UInt<1>
       wire j : UInt<1>
diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir
index 7bee8444..fb537303 100644
--- a/test/passes/expand-whens/two-when.fir
+++ b/test/passes/expand-whens/two-when.fir
@@ -3,7 +3,7 @@
 ; CHECK: Expand Whens
 circuit top :
    module top :
-      mem m :{ x : UInt<1>, y : UInt<1> }[2] 
+      cmem m :{ x : UInt<1>, y : UInt<1> }[2] 
       wire i : UInt<1>
       wire p : UInt<1>
       wire q : { x : UInt<1>, y : UInt<1> }
diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir
index d42e1dd5..43f61827 100644
--- a/test/passes/jacktest/Stack.fir
+++ b/test/passes/jacktest/Stack.fir
@@ -8,7 +8,7 @@ circuit Stack :
     output dataOut : UInt<32>
     input dataIn : UInt<32>
     
-    mem stack_mem : UInt<32>[16]
+    cmem stack_mem : UInt<32>[16]
     reg sp : UInt<5>
     on-reset sp := UInt<5>(0)
     reg out : UInt<32>
diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir
index bf7635fb..4e0e954c 100644
--- a/test/passes/jacktest/Tbl.fir
+++ b/test/passes/jacktest/Tbl.fir
@@ -7,7 +7,7 @@ circuit Tbl :
     output o : UInt<16>
     input we : UInt<1>
     
-    mem m : UInt<10>[256]
+    cmem m : UInt<10>[256]
     o := UInt<1>(0)
     when we : 
       accessor T_13 = m[i]
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index 875498d6..4d02bcf7 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -9,8 +9,8 @@ circuit Risc :
     input wrAddr : UInt<8>
     input wrData : UInt<32>
     
-    mem file : UInt<32>[256]
-    mem code : UInt<32>[256]
+    cmem file : UInt<32>[256]
+    cmem code : UInt<32>[256]
     reg pc : UInt<8>
     on-reset pc := UInt<8>(0)
     accessor inst = code[pc]
diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir
index 29663234..8fe1bc52 100644
--- a/test/passes/lower-to-ground/accessor.fir
+++ b/test/passes/lower-to-ground/accessor.fir
@@ -22,7 +22,7 @@ circuit top :
       ; CHECK: (a$0 a$1 a$2 a$3)[i] := c
       c := j
       
-      mem p : UInt<32>[4]
+      cmem p : UInt<32>[4]
       accessor t = p[i]
       ; CHECK: accessor t = p[i]
       j := t
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
index b7915c5d..c39850f4 100644
--- a/test/passes/lower-to-ground/nested-vec.fir
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -20,9 +20,9 @@ circuit top :
       ; CHECK: (a$0$y a$1$y)[i] := b$y
       j := b
 
-      mem m : { x : UInt<32>, y : UInt<32> }[2]
-      ; CHECK: mem m$x : UInt<32>[2]
-      ; CHECK: mem m$y : UInt<32>[2]
+      cmem m : { x : UInt<32>, y : UInt<32> }[2]
+      ; CHECK: cmem m$x : UInt<32>[2]
+      ; CHECK: cmem m$y : UInt<32>[2]
 
       accessor c = m[i] ; MALE
       ; CHECK: accessor c$x = m$x[i]