Added source indicators from FIRRTL files. Pass in -p i to get them printed. Should show up with check passes

4 files changed, 13 insertions, 13 deletions

diff --git a/test/chisel3/Datapath.fir b/test/chisel3/Datapath.fir
index bce95120..0727d53e 100644
--- a/test/chisel3/Datapath.fir
+++ b/test/chisel3/Datapath.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p cd | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -x X -p cdi | tee %s.out | FileCheck %s
 ; CHECK: Done!
 
 circuit Datapath : 
diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir
index 984b6acd..b87f954f 100644
--- a/test/passes/expand-accessors/accessor-mem.fir
+++ b/test/passes/expand-accessors/accessor-mem.fir
@@ -1,19 +1,19 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefg -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
 
 ;CHECK: Expand Accessors
 circuit top :
    module top :
-      mem m : UInt<32>[10][10][10]
-      wire i : UInt
+      mem m : UInt<32>[2][2][2]
+      wire i : UInt<4>
       accessor a = m[i] ;CHECK: accessor a = m[i]
-      accessor b = a[i] ;CHECK: b := (a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9])[i]
-      accessor c = b[i] ;CHECK: c := (b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9])[i]
+      accessor b = a[i] ;CHECK: b := (a[0] a[1])[i]
+      accessor c = b[i] ;CHECK: c := (b[0] b[1])[i]
       wire j : UInt
       j := c
 
       accessor x = m[i] ;CHECK: accessor x = m[i]
-      accessor y = x[i] ;CHECK: (x[0] x[1] x[2] x[3] x[4] x[5] x[6] x[7] x[8] x[9])[i] := y
-      accessor z = y[i] ;CHECK: (y[0] y[1] y[2] y[3] y[4] y[5] y[6] y[7] y[8] y[9])[i] := z
+      accessor y = x[i] ;CHECK: (x[0] x[1])[i] := y
+      accessor z = y[i] ;CHECK: (y[0] y[1])[i] := z
       z := j
 
 ; CHECK: Finished Expand Accessors
diff --git a/test/passes/jacktest/bundlewire.fir b/test/passes/jacktest/bundlewire.fir
index cd5b2dfe..cea54ed4 100644
--- a/test/passes/jacktest/bundlewire.fir
+++ b/test/passes/jacktest/bundlewire.fir
@@ -1,17 +1,17 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p cg | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -x X -p ct | tee %s.out | FileCheck %s
 
 ; CHECK: Expand Whens
 
 circuit TestLower : 
   module Inst :
-     input x : UInt
-     output y : UInt
+     input data : { w : UInt , x : UInt } 
+     input tag : { y : UInt, z : UInt }
   module TestLower : 
      mem m : {data : { w : UInt , x : UInt } tag : { y : UInt, z : UInt }}[8]
      wire index : UInt
      accessor r = m[index]
 
      inst i of Inst
-     i.x := r
+     i.data := r.data
 
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/lower-to-ground/test.fir b/test/passes/lower-to-ground/test.fir
index fb951bff..5f5f37fb 100644
--- a/test/passes/lower-to-ground/test.fir
+++ b/test/passes/lower-to-ground/test.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p cd | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -x X -p cdt | tee %s.out | FileCheck %s
 ; CHECK: Done!
 
 circuit Top :