First pass at a Verilog Backend. Not tested, but compiles and generates reasonable verilog. Requires inlining, future versions will instantiate modules

2 files changed, 46 insertions, 1 deletions

diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir
index 31314148..41aea1f4 100644
--- a/test/passes/resolve-genders/accessor.fir
+++ b/test/passes/resolve-genders/accessor.fir
@@ -3,7 +3,7 @@
 ;CHECK: Resolve Genders
 circuit top :
    module top :
-      wire m : UInt<32>[5][5][5]
+      wire m : UInt<32>[2][2][2]
       wire i : UInt
       accessor a = m[i] ;CHECK: accessor a = m@<g:m>[i@<g:m>]@<g:m>
       accessor b = a[i] ;CHECK: accessor b = a@<g:m>[i@<g:m>]@<g:m>
diff --git a/test/passes/to-verilog/gcd.fir b/test/passes/to-verilog/gcd.fir
new file mode 100644
index 00000000..170e7866
--- /dev/null
+++ b/test/passes/to-verilog/gcd.fir
@@ -0,0 +1,45 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+
+;CHECK: Verilog
+circuit top :
+   module subtracter :
+      input x : UInt
+      input y : UInt
+      output q : UInt
+      q := sub-wrap(x, y)
+   module gcd :
+      input a : UInt<16>
+      input b : UInt<16>
+      input e : UInt<1>
+      output z : UInt<16>
+      output v : UInt<1>
+      reg x : UInt
+      reg y : UInt
+      on-reset x := UInt(0)
+      on-reset y := UInt(42)
+      when gt(x, y) :
+         inst s of subtracter
+         s.x := x
+         s.y := y
+         x := s.q
+      else :
+         inst s2 of subtracter
+         s2.x := x
+         s2.y := y
+         y := s2.q
+      when e :
+         x := a
+         y := b
+      v := eq(v, UInt(0))
+      z := x
+   module top :
+      input a : UInt<16>
+      input b : UInt<16>
+      output z : UInt
+      inst i of gcd
+      i.a := a
+      i.b := b
+      i.e := UInt(1)
+      z := i.z
+;CHECK: Done!
+