| Age | Commit message (Expand) | Author |
|---|
| 2015-08-28 | Moved check type and check kind after check gender | azidar |
| 2015-08-26 | Fixed bug where firrtl was incorrectly judging the width of a bigint. #36 #37. | azidar |
| 2015-08-25 | Fixed bug in split expression that leaked connect statements out of a conditi... | azidar |
| 2015-08-25 | Added width check pass with tests. #22. | azidar |
| 2015-08-24 | Changed all tests to use verilog backend. | azidar |
| 2015-08-24 | Removed old chisel3 tests that all failed for syntax reasons. Tests should no... | azidar |
| 2015-08-20 | Added tests, cleaned up repo | azidar |
| 2015-08-20 | Added Poison node. Includes tests. #26. | azidar |
| 2015-08-20 | Added rsh test for const-prop | azidar |
| 2015-08-19 | Added new const propagation test | azidar |
| 2015-08-19 | Fixed width inference bug where constraints were propagating backwards. | azidar |
| 2015-08-18 | Updated shr test so it is an expected pass | azidar |
| 2015-08-18 | Fixed so its length is greater than what it connects to. Changed shr to be e... | azidar |
| 2015-08-17 | Removed leading zeros from UInt constants | azidar |
| 2015-08-17 | Fixed bug where equality between expressions was incorrect, leading to | azidar |
| 2015-08-17 | Added tests for shl and mem. Fixed bug in verilog output of mem size. | azidar |
| 2015-08-04 | Added check for reading from outputs with flips | azidar |
| 2015-08-04 | Added verilog keywords to uniquify them | azidar |
| 2015-08-04 | Fixed reading from instance's input ports. Fixed unique naming bug. | azidar |
| 2015-08-03 | Changed name mangling to use _ as a delin. Fixed bug in checking for | azidar |
| 2015-08-03 | Fixed performance bug in Split Expressions. Changed delin for connect indexed... | azidar |
| 2015-07-31 | Reading from output ports no longer causes errors | azidar |
| 2015-07-31 | Added errors for bulk connects where field names match but types/flips don't | azidar |
| 2015-07-31 | Updated tests to pipe from stderr to stdout | azidar |
| 2015-07-30 | Added module name to error messages. | azidar |
| 2015-07-30 | Updated error and feature tests. Fixed bug in detecting incorrect genders | azidar |
| 2015-07-30 | Added eqv for bitwise equality, and change eq to be arithmetic equality | azidar |
| 2015-07-30 | Updated lots of tests so they pass. Found one bug in expand whens | azidar |
| 2015-07-29 | Finished supporting Chisel 2.0 Ref Chip | Adam Izraelevitz |
| 2015-07-29 | Add bigint support. | Adam Izraelevitz |
| 2015-07-28 | Integrated bigint. Mostly works, but getting "cast" error for make Test. | Adam Izraelevitz |
| 2015-07-14 | Added tests for clocks. Added remove scope and special chars passes. Added te... | azidar |
| 2015-07-14 | Added clock support | azidar |
| 2015-07-14 | Pass most tests. The ones that do not pass are not expected to, yet | azidar |
| 2015-07-14 | Added chisel feedback to firrtl spec. Datapath_new triggers too large a width... | azidar |
| 2015-07-14 | Still partial commit, many tests pass. Many tests fail. | azidar |
| 2015-07-14 | In progress commit | azidar |
| 2015-06-12 | Major revisions to spec. Bumped to v0.1.2 | azidar |
| 2015-06-04 | Fixed fir files so they correctly compile to verilog! Front-end needs to gene... | azidar |
| 2015-06-03 | Fixed verilog backend bugs. Passes ALU. Fails Datapath | azidar |
| 2015-06-02 | Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ... | azidar |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. A... | azidar |
| 2015-05-29 | Added custom pass. Does not correctly run, stanza just spins. Requires debugg... | azidar |
| 2015-05-27 | Added sequential memories. mem no longer exists, must declare either cmem or ... | azidar |
| 2015-05-27 | Added external modules. Switched lower firrtl back to wire r; r := Register, ... | azidar |
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar |
| 2015-05-21 | Added pad pass, used for flo backend | azidar |
| 2015-05-20 | Added Pad pass to flo.stanza, which pads widths to make := and primops strict... | azidar |
| 2015-05-19 | Updated tests | azidar |
| 2015-05-18 | First pass at a Verilog Backend. Not tested, but compiles and generates reaso... | azidar |
