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2016-08-15Remove stanza (#231)Adam Izraelevitz
* Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before)
2016-04-08Fixed bug in Remove Accesses where a WSubAccess's index was not checked for ↵Adam Izraelevitz
accesses. Fixes #105
2016-02-09Added remaining check passes. Ready for open sourcingazidar
2016-02-09Changed stanza output of UInt/SInt to include widths. Made tests match ↵azidar
accordingly
2016-01-28Changed rmode to wmodeazidar
2016-01-28Updated all tests to passazidar
2016-01-28Changed register syntax for optional reset and init valuesazidar
2016-01-27Reworked readwriter typesazidar
2016-01-25Added verilog rename passazidar
2016-01-25Added isinvalid and validifazidar
2016-01-24Added muxing on passive aggregate typesazidar
2016-01-17Fixed error where memory of size 1 would create an index of size 0. This can ↵azidar
be fixed in the future with a pass that removes these memories
2016-01-16Added a bunch of tests and added firrtl-stanza and firrtl-scala to .gitignoreazidar
2016-01-16Fixed all tests so they either pass are marked as expected failuresazidar
2016-01-16Fixed a bunch of tests, and minor bugsazidar
2016-01-16WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit ↵azidar
roadblock in assigning clocked ports
2016-01-16Finished supporting nested accesses. Required some nuianced thinking. Pass ↵azidar
all feature tests. Deleted CondRead because it tested a problem we don't have any more
2016-01-16WIP, hit semantic bug in WSubAccessazidar
2016-01-16New memory works with verilog. Slowly changing tests and fixing bugs.azidar
Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
2016-01-16Finished adding clocks to Stop and Printazidar
2015-10-07Added Printf and Stop to firrtl. #23 #24.azidar
2015-09-30Make Link.fir reference relative path, so it doesn't need someone's ↵ducky
particular directory structure.
2015-09-24Updated conditional read exampleazidar
2015-09-01Added a conditional readport example, with new idea of representing a read ↵azidar
enable with muxing the index with poison bits
2015-08-24Changed all tests to use verilog backend.azidar
2015-08-20Added tests, cleaned up repoazidar
2015-08-20Added Poison node. Includes tests. #26.azidar
2015-08-17Removed leading zeros from UInt constantsazidar
2015-08-03Changed name mangling to use _ as a delin. Fixed bug in checking forazidar
invalid <> assignments.
2015-07-31Added errors for bulk connects where field names match but types/flips don'tazidar
2015-07-31Updated tests to pipe from stderr to stdoutazidar
2015-07-30Updated error and feature tests. Fixed bug in detecting incorrect gendersazidar
2015-07-30Updated lots of tests so they pass. Found one bug in expand whensazidar
2015-07-14Added tests for clocks. Added remove scope and special chars passes. Added ↵azidar
tests. Made more tests pass
2015-07-14Added clock supportazidar
2015-07-14Pass most tests. The ones that do not pass are not expected to, yetazidar
2015-06-02Added sequential/combinational memories. Started debugging verilog backend. ↵azidar
Added Long support so UInt(LARGENUMBER) works
2015-05-27Added sequential memories. mem no longer exists, must declare either cmem or ↵azidar
smem. Added firrtl-gensym utility to generate a hashmap of names
2015-05-27Added external modules. Switched lower firrtl back to wire r; r := Register, ↵azidar
instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed
2015-05-26Added <>. Added additional checks for primops. Added new chisel3 files.azidar
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