Updated all tests to pass

6 files changed, 18 insertions, 11 deletions

diff --git a/test/features/IsInvalid.fir b/test/features/IsInvalid.fir
index cf898fe9..f6766bf2 100644
--- a/test/features/IsInvalid.fir
+++ b/test/features/IsInvalid.fir
@@ -12,9 +12,10 @@ circuit Top :
        write-latency => 1
        reader => r
        writer => w
-       read-writer => rw
+       readwriter => rw
     wire x : { w : UInt<42>, x : UInt<20>}
-    reg c : { w : UInt<42>, x : UInt<20>},clk,reset,x
+    reg c : { w : UInt<42>, x : UInt<20>},clk with :
+       reset => (reset,x)
     inst other of Other
    
     clk is invalid
diff --git a/test/features/Poison.fir b/test/features/Poison.fir
index a4cb1a25..a2e0acfb 100644
--- a/test/features/Poison.fir
+++ b/test/features/Poison.fir
@@ -16,7 +16,7 @@ circuit Poison :
        write-latency => 2
        reader => r
        writer => w
-       read-writer => rw
+       readwriter => rw
     m.r.addr <= index
     m.r.en <= UInt(1)
     m.r.clk <= clk
diff --git a/test/features/Printf.fir b/test/features/Printf.fir
index 4e8682ff..d4d2f77d 100644
--- a/test/features/Printf.fir
+++ b/test/features/Printf.fir
@@ -17,5 +17,5 @@ circuit Top :
 ;CHECK: printf(clk, en, "Hello World!\n")
 ;CHECK: printf(clk, en, "Hello World! %x\n", x.y)
 ;CHECK: printf(clk, and(p, en), "In consequence\n")
-;CHECK: printf(clk, and(eqv(p, UInt("h0")), en), "In alternate\n")   
+;CHECK: printf(clk, and(eq(p, UInt("h0")), en), "In alternate\n")   
 ;CHECK: Done!
diff --git a/test/features/Queue.fir b/test/features/Queue.fir
index 9b19caf4..3ce58e31 100644
--- a/test/features/Queue.fir
+++ b/test/features/Queue.fir
@@ -7,6 +7,7 @@ circuit Queue :
     input clk : Clock
     input reset : UInt<1>
   
-    reg r : UInt<10>,clk,reset,in
+    reg r : UInt<10>,clk with :
+       reset => (reset,in)
     r <= in
     out <= r
diff --git a/test/features/TwoClocks.fir b/test/features/TwoClocks.fir
index 6562d3e1..3753ee8d 100644
--- a/test/features/TwoClocks.fir
+++ b/test/features/TwoClocks.fir
@@ -5,14 +5,18 @@ circuit Top :
     input clk2 : Clock
     input reset1 : UInt<1>
     input reset2 : UInt<1>
-    reg src : UInt<10>, clk1, reset1, UInt(0)
-    reg sink : UInt<10>, clk2, reset2, UInt(0)
+    reg src : UInt<10>, clk1 with :
+       reset => ( reset1, UInt(0))
+    reg sink : UInt<10>, clk2 with :
+       reset => ( reset2, UInt(0))
 
-    src <= addw(src,UInt(1))
+    src <= add(src,UInt(1))
 
-    reg sync_A : UInt<10>, clk2, reset2, UInt(0)
+    reg sync_A : UInt<10>, clk2 with :
+       reset => ( reset2, UInt(0))
     sync_A <= src
-    reg sync_B : UInt<10>, clk2, reset2, UInt(0)
+    reg sync_B : UInt<10>, clk2 with :
+       reset => ( reset2, UInt(0))
     sync_B <= sync_A
 
     sink <= sync_B
diff --git a/test/features/VerilogReg.fir b/test/features/VerilogReg.fir
index 33c4417f..96022933 100644
--- a/test/features/VerilogReg.fir
+++ b/test/features/VerilogReg.fir
@@ -7,7 +7,8 @@ circuit Poison :
     input p1 : UInt<1>
     input p2 : UInt<1>
     input p3 : UInt<1>
-    reg r : UInt<32>,clk,reset,r
+    reg r : UInt<32>,clk with :
+       reset => (reset,r)
     when p1 :
        r <= UInt(1)
     when p2 :