diff options
| author | azidar | 2016-01-24 16:30:50 -0800 |
|---|---|---|
| committer | azidar | 2016-01-24 16:30:50 -0800 |
| commit | 8265e2e67e39f2d313a74bccb6dd45d85f706f3a (patch) | |
| tree | 744a5eea0e86a43aaeb720fc545bcfe80840b139 /test/features | |
| parent | 63b3668414bfea1c3bdd651a552d5fa7b5d6b9c4 (diff) | |
Added muxing on passive aggregate types
Diffstat (limited to 'test/features')
| -rw-r--r-- | test/features/InitAccessor.fir | 2 | ||||
| -rw-r--r-- | test/features/MuxBundle.fir | 16 |
2 files changed, 17 insertions, 1 deletions
diff --git a/test/features/InitAccessor.fir b/test/features/InitAccessor.fir index 5a81a62e..6261ec01 100644 --- a/test/features/InitAccessor.fir +++ b/test/features/InitAccessor.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s ;CHECK: Done! circuit Top : diff --git a/test/features/MuxBundle.fir b/test/features/MuxBundle.fir new file mode 100644 index 00000000..764078d5 --- /dev/null +++ b/test/features/MuxBundle.fir @@ -0,0 +1,16 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +;CHECK: Expand Connects +circuit Top : + module Top : + input a: {w:UInt<42>,x:UInt<20>} + input b: {w:UInt<42>,x:UInt<20>} + input c: {w:UInt<42>,x:UInt<20>} + input p : UInt<1> + output d: {w:UInt<42>,x:UInt<20>} + d <= mux(p,mux(p,a,b),c) +;CHECK: d.w <= mux(p, mux(p, a.w, b.w), c.w) +;CHECK: d.x <= mux(p, mux(p, a.x, b.x), c.x) + +;CHECK: Finished Expand Connects +;CHECK: Done! + |