diff options
| author | azidar | 2015-07-10 13:25:21 -0700 |
|---|---|---|
| committer | azidar | 2015-07-14 11:29:55 -0700 |
| commit | 0bfb3618b654a4082cc2780887b3ca32e374f455 (patch) | |
| tree | 230b7cbc96589be229e6f3d87f21300fb8fd84c3 /test/features | |
| parent | 0d63d521de85d1c6b9109e019101d0f575d063f7 (diff) | |
Added clock support
Diffstat (limited to 'test/features')
| -rw-r--r-- | test/features/SeqMem.fir | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/test/features/SeqMem.fir b/test/features/SeqMem.fir index 4b346ea9..4714ad4f 100644 --- a/test/features/SeqMem.fir +++ b/test/features/SeqMem.fir @@ -2,6 +2,7 @@ ;CHECK: Done! circuit Top : module Top : + input clk : Clock wire i : UInt<5> i := UInt(1) wire i0 : UInt<5> @@ -9,14 +10,14 @@ circuit Top : i0 := UInt(10) - cmem m-com : UInt<128>[32] + cmem m-com : UInt<128>[32], clk infer accessor r-com = m-com[i] infer accessor w-com = m-com[i] j := r-com w-com := j - smem m-seq : UInt<128>[32] + smem m-seq : UInt<128>[32], clk infer accessor r-seq = m-seq[i] infer accessor w-seq = m-seq[i] j := r-seq |