From 0bfb3618b654a4082cc2780887b3ca32e374f455 Mon Sep 17 00:00:00 2001
From: azidar
Date: Fri, 10 Jul 2015 13:25:21 -0700
Subject: Added clock support

---
 test/features/SeqMem.fir | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'test/features')

diff --git a/test/features/SeqMem.fir b/test/features/SeqMem.fir
index 4b346ea9..4714ad4f 100644
--- a/test/features/SeqMem.fir
+++ b/test/features/SeqMem.fir
@@ -2,6 +2,7 @@
 ;CHECK: Done!
 circuit Top : 
   module Top : 
+    input clk : Clock
     wire i : UInt<5>
     i := UInt(1)
     wire i0 : UInt<5>
@@ -9,14 +10,14 @@ circuit Top :
 
     i0 := UInt(10)
 
-    cmem m-com : UInt<128>[32]
+    cmem m-com : UInt<128>[32], clk
     infer accessor r-com = m-com[i]
     infer accessor w-com = m-com[i]
     j := r-com
     w-com := j
 
 
-    smem m-seq : UInt<128>[32]
+    smem m-seq : UInt<128>[32], clk
     infer accessor r-seq = m-seq[i]
     infer accessor w-seq = m-seq[i]
     j := r-seq
-- 
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