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authorazidar2015-07-10 13:25:21 -0700
committerazidar2015-07-14 11:29:55 -0700
commit0bfb3618b654a4082cc2780887b3ca32e374f455 (patch)
tree230b7cbc96589be229e6f3d87f21300fb8fd84c3
parent0d63d521de85d1c6b9109e019101d0f575d063f7 (diff)
Added clock support
Diffstat
-rw-r--r--TODO24
-rw-r--r--notes/frontend-notes.04.16.15.txt11
-rw-r--r--src/main/stanza/compilers.stanza4
-rw-r--r--src/main/stanza/custom-compiler.stanza2
-rw-r--r--src/main/stanza/custom-passes.stanza2
-rw-r--r--src/main/stanza/errors.stanza31
-rw-r--r--src/main/stanza/firrtl-ir.stanza4
-rw-r--r--src/main/stanza/flo.stanza1
-rw-r--r--src/main/stanza/ir-parser.stanza47
-rw-r--r--src/main/stanza/ir-utils.stanza40
-rw-r--r--src/main/stanza/passes.stanza157
-rw-r--r--src/main/stanza/verilog.stanza79
-rw-r--r--test/chisel3/ALUTop.fir28
-rw-r--r--test/chisel3/Control.fir108
-rw-r--r--test/chisel3/Core.fir1274
-rw-r--r--test/chisel3/Datapath.fir174
-rw-r--r--test/features/SeqMem.fir5
-rw-r--r--test/passes/expand-accessors/accessor-mem.fir3
18 files changed, 1024 insertions, 970 deletions
diff --git a/TODO b/TODO
index edc3fe17..2ba5f2b4 100644
--- a/TODO
+++ b/TODO
@@ -3,22 +3,22 @@
================================================
======== Current Tasks ========
-Add/Update Unit Tests for each pass
- Check after each pass
- write test that checks instance types are correctly lowered
+change parser to accept subword, but error
+--Merge with master
+
+Tests:
+ Lowering for instance types with bundle ports
+ More prefix tests
+ Expand-when semantics
+ Ensure module names are unique
+ Large width of dshl
+
fix expand-whens to have correct semantics
-ensure module names are unique
-add check that limits size of width of dshl
-add efficient prefix checker
update high/low firrtl checks
-add clock type
-add clock, reset to reg, mem etc
+add efficient prefix checker
need a multi-clock domain example
need an annotation example
-change parser to accept subword, but error
-
-move width inference earlier
- Required for subword assignment, consistent vec width inference, and supporting the new constructs of tobits/frombits
+move width inference earlier (required for subword assignment, consistent vec width inference, and supporting the new constructs of tobits/frombits)
Temp elimination needs to count # uses
Declared references needs to understand scope <= check in high form check
Check for recursively defined instances
diff --git a/notes/frontend-notes.04.16.15.txt b/notes/frontend-notes.04.16.15.txt
index 23da75d9..fb7c1af9 100644
--- a/notes/frontend-notes.04.16.15.txt
+++ b/notes/frontend-notes.04.16.15.txt
@@ -1,6 +1,17 @@
======= Fixes to Jonathan's Front-end ======
== TODO ==
+convert -> cvt
+as-UInt -> asUInt
+as-SInt -> asSInt
+add-wrap -> addw
+sub-wrap -> subw
+bit-and -> and
+bit-or -> or
+bit-xor -> xor
+
+
+
Fixing chisel3 front-end bugs:
LFSR16: "concat" -> "cat"
MemorySearch: name collision with node done and output done
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index 2f6329dc..c458f1e1 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -15,7 +15,7 @@ public defmethod passes (c:StandardFlo) -> List<Pass> :
CheckHighForm(expand-delin)
;; TempElimination()
ToWorkingIR()
- MakeExplicitReset()
+ ;; MakeExplicitReset()
ResolveKinds()
CheckKinds()
InferTypes()
@@ -45,7 +45,7 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
CheckHighForm(expand-delin)
TempElimination()
ToWorkingIR()
- MakeExplicitReset()
+ ;; MakeExplicitReset()
ResolveKinds()
CheckKinds()
InferTypes()
diff --git a/src/main/stanza/custom-compiler.stanza b/src/main/stanza/custom-compiler.stanza
index 773b63ca..91732f22 100644
--- a/src/main/stanza/custom-compiler.stanza
+++ b/src/main/stanza/custom-compiler.stanza
@@ -17,7 +17,7 @@ public defmethod passes (c:InstrumentedVerilog) -> List<Pass> :
CheckHighForm(expand-delin)
TempElimination()
ToWorkingIR()
- MakeExplicitReset()
+ ;; MakeExplicitReset()
ResolveKinds()
CheckKinds()
InferTypes()
diff --git a/src/main/stanza/custom-passes.stanza b/src/main/stanza/custom-passes.stanza
index 6c1e58f6..4904d6d1 100644
--- a/src/main/stanza/custom-passes.stanza
+++ b/src/main/stanza/custom-passes.stanza
@@ -70,7 +70,7 @@ defn when-coverage (port-name:Symbol, reg-name:Symbol, instrument?:HashTable<Sym
val w-ls = to-list $ when-bits
if length(w-ls) != 0 :
val reg-ref = Ref(reg-name,UIntType(IntWidth(length(w-ls))))
- add{logic,_} $ DefRegister(FileInfo(),name(reg-ref),type(reg-ref))
+ ;add{logic,_} $ DefRegister(FileInfo(),name(reg-ref),type(reg-ref)) TODO add clock and reset
add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(to-long $ 0,IntWidth(length(w-ls))))
for (x in w-ls, i in 0 to false) do :
add{logic,_} $ DefWire(FileInfo(),name(x),type(x))
diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza
index e726fd00..b92939d7 100644
--- a/src/main/stanza/errors.stanza
+++ b/src/main/stanza/errors.stanza
@@ -24,7 +24,6 @@ defpackage firrtl/errors :
;AFTER ??????
; o No combinational loops
-; o cannot connect to a pad, or a register. only connct to a reference
;================= High Form Check ==========================
; * Subexps of Subfield and Index can only be subfields, index, or refs
@@ -32,7 +31,6 @@ defpackage firrtl/errors :
; * A module has the same name as main of circuit
; * mems cannot be a bundle with flips
; * instance module must have the same name as a defined module
-; * reset must be UInt<1>
; * Unique names per module
; * No name can be a prefix of any other name.
; * all references are declared
@@ -88,9 +86,9 @@ defn ModuleNotDefined (info:FileInfo, name:Symbol) :
PassException $ string-join $
[info ": Module " name " is not defined."]
-defn WrongReset (info:FileInfo, name:Symbol) :
- PassException $ string-join $
- [info ": Module " name " has a reset that is not of type UInt<1>."]
+;defn WrongReset (info:FileInfo, name:Symbol) :
+; PassException $ string-join $
+; [info ": Module " name " has a reset that is not of type UInt<1>."]
defn IncorrectNumArgs (info:FileInfo, op:Symbol, n:Int) :
PassException $ string-join $
@@ -324,15 +322,15 @@ public defn check-high-form (c:Circuit,sym:Symbol) -> Circuit :
names[name(m)] = true
for p in ports(m) do :
names[name(p)] = true
- if name(p) == `reset :
- if direction(p) == OUTPUT :
- add(errors,WrongReset(info!(m),name(m)))
- else :
- if type(p) typeof UIntType :
- if width(type(p) as UIntType) != IntWidth(1) :
- add(errors,WrongReset(info!(m),name(m)))
- else :
- add(errors,WrongReset(info!(m),name(m)))
+ ;if name(p) == `reset :
+ ; if direction(p) == OUTPUT :
+ ; add(errors,WrongReset(info!(m),name(m)))
+ ; else :
+ ; if type(p) typeof UIntType :
+ ; if width(type(p) as UIntType) != IntWidth(1) :
+ ; add(errors,WrongReset(info!(m),name(m)))
+ ; else :
+ ; add(errors,WrongReset(info!(m),name(m)))
map(check-high-form-t{info(p),_},type(p))
map(check-high-form-w{info(p),_},type(p))
@@ -436,6 +434,8 @@ public defn check-kinds (c:Circuit) -> Circuit :
; o node's value cannot be a bundle with a flip in it
; o := has same types
; o 2nd arg in dshr/l must be UInt, in general do primops
+; o clock must be ClockType
+; o reset must be UInt<1>
public defstruct CheckTypes <: Pass
public defmethod pass (b:CheckTypes) -> (Circuit -> Circuit) : check-types
@@ -499,6 +499,7 @@ defn NodeWithFlips (info:FileInfo) :
;---------------- Helper Functions --------------
defmethod equal? (t1:Type,t2:Type) -> True|False :
match(t1,t2) :
+ (t1:ClockType,t2:ClockType) : true
(t1:UIntType,t2:UIntType) : true
(t1:SIntType,t2:SIntType) : true
(t1:BundleType,t2:BundleType) :
@@ -648,7 +649,6 @@ defn gender (s:DefAccessor) -> Gender :
INFER : UNKNOWN-GENDER
RDWR : BI-GENDER
-
;----------------- Check Genders Pass ---------------------
public defn check-genders (c:Circuit) -> Circuit :
@@ -728,6 +728,7 @@ public defn check-genders (c:Circuit) -> Circuit :
; o no accessors
; o only vecs are for memories
; o no bundles (future, will have them for mems)
+; o only predicated conditional connects
public defstruct CheckLowForm <: Pass
public defmethod pass (b:CheckLowForm) -> (Circuit -> Circuit) : check-low-form
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index b698bae2..b9d2cee4 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -101,6 +101,8 @@ public defstruct DefRegister <: Stmt :
info: FileInfo with: (as-method => true)
name: Symbol
type: Type
+ clock: Expression
+ reset: Expression
public defstruct DefInstance <: Stmt : ;LOW
info: FileInfo with: (as-method => true)
name: Symbol
@@ -110,6 +112,7 @@ public defstruct DefMemory <: Stmt : ;LOW
name: Symbol
type: VectorType
seq?: True|False
+ clock: Expression
public defstruct DefNode <: Stmt : ;LOW
info: FileInfo with: (as-method => true)
name: Symbol
@@ -151,6 +154,7 @@ public defstruct BundleType <: Type :
public defstruct VectorType <: Type :
type: Type
size: Int
+public defstruct ClockType <: Type
public defstruct UnknownType <: Type
public defstruct Field :
diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza
index 9f4cdc8c..d8fe705f 100644
--- a/src/main/stanza/flo.stanza
+++ b/src/main/stanza/flo.stanza
@@ -69,6 +69,7 @@ defn prim-width (type:Type) -> Int :
match(type) :
(t:UIntType) : sane-width(width(t))
(t:SIntType) : sane-width(width(t))
+ (t:ClockType) : 1
(t) : error("Bad prim width type")
defn sizeof (in: Int) -> Int :
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index f85ff7c9..96c50c3c 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -38,8 +38,8 @@ OPERATORS[`div] = DIV-OP
OPERATORS[`mod] = MOD-OP
OPERATORS[`quo] = QUO-OP
OPERATORS[`rem] = REM-OP
-OPERATORS[`add-wrap] = ADD-WRAP-OP
-OPERATORS[`sub-wrap] = SUB-WRAP-OP
+OPERATORS[`addw] = ADD-WRAP-OP
+OPERATORS[`subw] = SUB-WRAP-OP
OPERATORS[`lt] = LESS-OP
OPERATORS[`leq] = LESS-EQ-OP
OPERATORS[`gt] = GREATER-OP
@@ -49,20 +49,20 @@ OPERATORS[`neq] = NEQUAL-OP
OPERATORS[`mux] = MUX-OP
OPERATORS[`pad] = PAD-OP
OPERATORS[`neg] = NEG-OP
-OPERATORS[`as-UInt] = AS-UINT-OP
-OPERATORS[`as-SInt] = AS-SINT-OP
+OPERATORS[`asUInt] = AS-UINT-OP
+OPERATORS[`asSInt] = AS-SINT-OP
OPERATORS[`dshl] = DYN-SHIFT-LEFT-OP
OPERATORS[`dshr] = DYN-SHIFT-RIGHT-OP
OPERATORS[`shl] = SHIFT-LEFT-OP
OPERATORS[`shr] = SHIFT-RIGHT-OP
-OPERATORS[`convert] = CONVERT-OP
-OPERATORS[`bit-and-reduce] = BIT-AND-REDUCE-OP
-OPERATORS[`bit-or-reduce] = BIT-OR-REDUCE-OP
-OPERATORS[`bit-xor-reduce] = BIT-XOR-REDUCE-OP
-OPERATORS[`bit-not] = BIT-NOT-OP
-OPERATORS[`bit-and] = BIT-AND-OP
-OPERATORS[`bit-or] = BIT-OR-OP
-OPERATORS[`bit-xor] = BIT-XOR-OP
+OPERATORS[`cvt] = CONVERT-OP
+OPERATORS[`andr] = BIT-AND-REDUCE-OP
+OPERATORS[`orr] = BIT-OR-REDUCE-OP
+OPERATORS[`xorr] = BIT-XOR-REDUCE-OP
+OPERATORS[`not] = BIT-NOT-OP
+OPERATORS[`and] = BIT-AND-OP
+OPERATORS[`or] = BIT-OR-OP
+OPERATORS[`xor] = BIT-XOR-OP
OPERATORS[`cat] = CONCAT-OP
OPERATORS[`bit] = BIT-SELECT-OP
OPERATORS[`bits] = BITS-SELECT-OP
@@ -187,7 +187,10 @@ defsyntax firrtl :
inttype = (SInt<?w:#width$>) : SIntType(w)
inttype = (SInt) : SIntType(UnknownWidth())
+ clktype = (Clock) : ClockType()
+
type = (?t:#typeterm ?ops:#typeop ...) : apply-suffix-ops(t, ops)
+ type = (?t:#clktype) : t
typeop = ((@get ?size:#int$)) : (fn (t) : VectorType(t, size))
typeterm = (?t:#inttype) : t
@@ -213,16 +216,16 @@ defsyntax firrtl :
;Main Statement Productions
defrule statements :
stmt = (wire ?name:#id! #:! ?t:#type!) : DefWire(first-info(form),name, t)
- stmt = (reg ?name:#id! #:! ?t:#type!) : DefRegister(first-info(form),name, t)
- stmt = (cmem ?name:#id! #:! ?t:#vectype!) : DefMemory(first-info(form),name, t, false)
- stmt = (smem ?name:#id! #:! ?t:#vectype!) : DefMemory(first-info(form),name, t, true)
- stmt = (inst ?name:#id! #of! ?m:#ref!) : DefInstance(first-info(form),name, m)
- stmt = (node ?name:#id! #=! ?e:#exp!) : DefNode(first-info(form),name, e)
- stmt = (on-reset ?x:#exp := ?y:#exp!) : OnReset(first-info(form),x, y)
- stmt = (read accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name, s, i,READ)
- stmt = (write accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name, s, i,WRITE)
- stmt = (infer accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name, s, i,INFER)
- stmt = (rdwr accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name, s, i,RDWR)
+ stmt = (reg ?name:#id! #:! ?t:#type! ?clk:#exp! ?reset:#exp!) : DefRegister(first-info(form),name, t,clk,reset)
+ stmt = (cmem ?name:#id! #:! ?t:#vectype! ?clk:#exp!) : DefMemory(first-info(form),name, t, false, clk)
+ stmt = (smem ?name:#id! #:! ?t:#vectype! ?clk:#exp!) : DefMemory(first-info(form),name, t, true, clk)
+ stmt = (inst ?name:#id! #of! ?m:#ref!) : DefInstance(first-info(form),name,m)
+ stmt = (node ?name:#id! #=! ?e:#exp!) : DefNode(first-info(form),name,e)
+ stmt = (onreset ?x:#exp := ?y:#exp!) : OnReset(first-info(form),x,y)
+ stmt = (read accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name,s,i,READ)
+ stmt = (write accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name,s,i,WRITE)
+ stmt = (infer accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name,s,i,INFER)
+ stmt = (rdwr accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name,s, i,RDWR)
stmt = (?s:#stmt/when) : s
stmt = (?x:#exp := ?y:#exp!) : Connect(first-info(form),x, y)
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index 8e65005f..bd8a0fd6 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -128,8 +128,8 @@ defmethod print (o:OutputStream, op:PrimOp) :
MOD-OP : "mod"
QUO-OP : "quo"
REM-OP : "rem"
- ADD-WRAP-OP : "add-wrap"
- SUB-WRAP-OP : "sub-wrap"
+ ADD-WRAP-OP : "addw"
+ SUB-WRAP-OP : "subw"
LESS-OP : "lt"
LESS-EQ-OP : "leq"
GREATER-OP : "gt"
@@ -138,21 +138,21 @@ defmethod print (o:OutputStream, op:PrimOp) :
NEQUAL-OP : "neq"
MUX-OP : "mux"
PAD-OP : "pad"
- AS-UINT-OP : "as-UInt"
- AS-SINT-OP : "as-SInt"
+ AS-UINT-OP : "asUInt"
+ AS-SINT-OP : "asSInt"
DYN-SHIFT-LEFT-OP : "dshl"
DYN-SHIFT-RIGHT-OP : "dshr"
SHIFT-LEFT-OP : "shl"
SHIFT-RIGHT-OP : "shr"
- CONVERT-OP : "convert"
+ CONVERT-OP : "cvt"
NEG-OP : "neg"
- BIT-NOT-OP : "bit-not"
- BIT-AND-OP : "bit-and"
- BIT-OR-OP : "bit-or"
- BIT-XOR-OP : "bit-xor"
- BIT-AND-REDUCE-OP : "bit-and-reduce"
- BIT-OR-REDUCE-OP : "bit-or-reduce"
- BIT-XOR-REDUCE-OP : "bit-xor-reduce"
+ BIT-NOT-OP : "not"
+ BIT-AND-OP : "and"
+ BIT-OR-OP : "or"
+ BIT-XOR-OP : "xor"
+ BIT-AND-REDUCE-OP : "andr"
+ BIT-OR-REDUCE-OP : "orr"
+ BIT-XOR-REDUCE-OP : "xorr"
CONCAT-OP : "cat"
BIT-SELECT-OP : "bit"
BITS-SELECT-OP : "bits"
@@ -176,10 +176,10 @@ defmethod print (o:OutputStream, c:Stmt) :
(c:DefWire) :
print-all(o,["wire " name(c) " : " type(c)])
(c:DefRegister) :
- print-all(o,["reg " name(c) " : " type(c)])
+ print-all(o,["reg " name(c) " : " type(c) ", " clock(c) ", " reset(c)])
(c:DefMemory) :
- if seq?(c) : print-all(o,["smem " name(c) " : " type(c)])
- else : print-all(o,["cmem " name(c) " : " type(c)])
+ if seq?(c) : print-all(o,["smem " name(c) " : " type(c) ", " clock(c)])
+ else : print-all(o,["cmem " name(c) " : " type(c) ", " clock(c)])
(c:DefInstance) :
print-all(o,["inst " name(c) " of " module(c)])
(c:DefNode) :
@@ -206,7 +206,7 @@ defmethod print (o:OutputStream, c:Stmt) :
(c:BulkConnect) :
print-all(o, [loc(c) " <> " exp(c)])
(c:OnReset) :
- print-all(o, ["on-reset " loc(c) " := " exp(c)])
+ print-all(o, ["onreset " loc(c) " := " exp(c)])
(c:EmptyStmt) :
print(o, "skip")
if not c typeof Conditionally|Begin|EmptyStmt : print-debug(o,c)
@@ -215,6 +215,8 @@ defmethod print (o:OutputStream, t:Type) :
match(t) :
(t:UnknownType) :
print(o, "?")
+ (t:ClockType) :
+ print(o, "Clock")
(t:UIntType) :
match(width(t)) :
(w:UnknownWidth) : print-all(o, ["UInt"])
@@ -290,6 +292,8 @@ public defmulti map<?T> (f: Expression -> Expression, c:?T&Stmt) -> T
defmethod map (f: Expression -> Expression, c:Stmt) -> Stmt :
match(c) :
(c:DefAccessor) : DefAccessor(info(c),name(c), f(source(c)), f(index(c)),acc-dir(c))
+ (c:DefRegister) : DefRegister(info(c),name(c), type(c), f(clock(c)), f(reset(c)))
+ (c:DefMemory) : DefMemory(info(c),name(c), type(c), seq?(c), f(clock(c)))
(c:DefNode) : DefNode(info(c),name(c), f(value(c)))
(c:DefInstance) : DefInstance(info(c),name(c), f(module(c)))
(c:Conditionally) : Conditionally(info(c),f(pred(c)), conseq(c), alt(c))
@@ -332,8 +336,8 @@ public defmulti map<?T> (f: Type -> Type, c:?T&Stmt) -> T
defmethod map (f: Type -> Type, c:Stmt) -> Stmt :
match(c) :
(c:DefWire) : DefWire(info(c),name(c),f(type(c)))
- (c:DefRegister) : DefRegister(info(c),name(c),f(type(c)))
- (c:DefMemory) : DefMemory(info(c),name(c),f(type(c)) as VectorType,seq?(c))
+ (c:DefRegister) : DefRegister(info(c),name(c),f(type(c)),clock(c),reset(c))
+ (c:DefMemory) : DefMemory(info(c),name(c),f(type(c)) as VectorType,seq?(c),clock(c))
(c) : c
public defmulti mapr<?T> (f: Width -> Width, t:?T&Type) -> T
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 95f2f33d..a20bec5a 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -12,7 +12,7 @@ public val standard-passes = to-list $ [
CheckHighForm(expand-delin)
TempElimination()
ToWorkingIR()
- MakeExplicitReset()
+ ;MakeExplicitReset()
ResolveKinds()
CheckKinds()
InferTypes()
@@ -350,47 +350,48 @@ defn to-working-ir (c:Circuit) :
; If reset is not explicitly passed to instantiations, then this
; pass autmatically connects the parent module's reset to the
; instantiation's reset
-public defstruct MakeExplicitReset <: Pass
-public defmethod pass (b:MakeExplicitReset) -> (Circuit -> Circuit) : make-explicit-reset
-public defmethod name (b:MakeExplicitReset) -> String : "Make Explicit Reset"
-public defmethod short-name (b:MakeExplicitReset) -> String : "make-explicit-reset"
-
-defn make-explicit-reset (c:Circuit) :
- defn find-explicit (c:Circuit) -> List<Symbol> :
- defn explicit? (m:Module) -> True|False :
- for p in ports(m) any? :
- name(p) == `reset
- val explicit-reset = Vector<Symbol>()
- for m in modules(c) do:
- if explicit?(m) : add(explicit-reset,name(m))
- to-list(explicit-reset)
-
- defn make-explicit (m:Module, explicit-reset:List<Symbol>) -> Module :
- defn route-reset (s:Stmt) -> Stmt :
- match(s) :
- (s:DefInstance) :
- val iref = WSubfield(WRef(name(s), UnknownType(), InstanceKind(), UNKNOWN-GENDER),`reset,UnknownType(),UNKNOWN-GENDER)
- val pref = WRef(`reset, UnknownType(), PortKind(), MALE)
- Begin(to-list([s,Connect(info(s),iref,pref)]))
- (s) : map(route-reset,s)
-
- var ports! = ports(m)
- if not contains?(explicit-reset,name(m)) :
- ports! = append(ports(m),list(Port(FileInfo(),`reset,INPUT,UIntType(IntWidth(1)))))
- match(m) :
- (m:InModule) :
- val body! = route-reset(body(m))
- InModule(info(m),name(m),ports!,body!)
- (m:ExModule) : ExModule(info(m),name(m),ports!)
-
- defn make-explicit-reset (m:Module, c:Circuit) -> Module :
- val explicit-reset = find-explicit(c)
- make-explicit(m,explicit-reset)
- Circuit(info(c),modules*, main(c)) where :
- val modules* =
- for m in modules(c) map :
- make-explicit-reset(m,c)
+;public defstruct MakeExplicitReset <: Pass
+;public defmethod pass (b:MakeExplicitReset) -> (Circuit -> Circuit) : make-explicit-reset
+;public defmethod name (b:MakeExplicitReset) -> String : "Make Explicit Reset"
+;public defmethod short-name (b:MakeExplicitReset) -> String : "make-explicit-reset"
+;
+;defn make-explicit-reset (c:Circuit) :
+; defn find-explicit (c:Circuit) -> List<Symbol> :
+; defn explicit? (m:Module) -> True|False :
+; for p in ports(m) any? :
+; name(p) == `reset
+; val explicit-reset = Vector<Symbol>()
+; for m in modules(c) do:
+; if explicit?(m) : add(explicit-reset,name(m))
+; to-list(explicit-reset)
+;
+; defn make-explicit (m:Module, explicit-reset:List<Symbol>) -> Module :
+; defn route-reset (s:Stmt) -> Stmt :
+; match(s) :
+; (s:DefInstance) :
+; val iref = WSubfield(WRef(name(s), UnknownType(), InstanceKind(), UNKNOWN-GENDER),`reset,UnknownType(),UNKNOWN-GENDER)
+; val pref = WRef(`reset, UnknownType(), PortKind(), MALE)
+; Begin(to-list([s,Connect(info(s),iref,pref)]))
+; (s) : map(route-reset,s)
+;
+; var ports! = ports(m)
+; if not contains?(explicit-reset,name(m)) :
+; ports! = append(ports(m),list(Port(FileInfo(),`reset,INPUT,UIntType(IntWidth(1)))))
+; match(m) :
+; (m:InModule) :
+; val body! = route-reset(body(m))
+; InModule(info(m),name(m),ports!,body!)
+; (m:ExModule) : ExModule(info(m),name(m),ports!)
+;
+; defn make-explicit-reset (m:Module, c:Circuit) -> Module :
+; val explicit-reset = find-explicit(c)
+; make-explicit(m,explicit-reset)
+;
+; Circuit(info(c),modules*, main(c)) where :
+; val modules* =
+; for m in modules(c) map :
+; make-explicit-reset(m,c)
;=============== Resolve Kinds =============================
; It is useful for the compiler to know information about
@@ -852,7 +853,7 @@ defn lower (body:Stmt) -> Stmt :
DefWire(info(s),name(x),type(x))
(s:DefRegister) : Begin{_} $
for x in generate-entry(name(s),type(s)) map :
- DefRegister(info(s),name(x),type(x))
+ DefRegister(info(s),name(x),type(x),clock(s),reset(s))
(s:DefInstance) :
val fields =
for f in fields(type(module(s)) as BundleType) map-append :
@@ -866,7 +867,7 @@ defn lower (body:Stmt) -> Stmt :
DefNode(info(s),name(s),exp(x))
(s:DefMemory) : Begin $
for x in generate-entry(name(s),type(type(s))) map :
- DefMemory(info(s),name(x),VectorType(type(x),size(s)), seq?(s))
+ DefMemory(info(s),name(x),VectorType(type(x),size(s)),seq?(s),clock(s))
(s:DefAccessor) :
val ls = generate-entry(name(s),type(s))
val rs = generate-entry(name(source(s) as WRef),type(s))
@@ -1265,14 +1266,13 @@ defn get-write-enable (sv:SymbolicValue) -> SymbolicValue :
(sv: SVNul) : SVExp(zero)
(sv) : sv
-defn merge-resets (assign:HashTable<Symbol,SymbolicValue>, resets:HashTable<Symbol,SymbolicValue>) -> HashTable<Symbol,SymbolicValue> :
+defn merge-resets (assign:HashTable<Symbol,SymbolicValue>, resets:HashTable<Symbol,SymbolicValue>, rsignals:HashTable<Symbol,Expression>) -> HashTable<Symbol,SymbolicValue> :
val table = HashTable<Symbol,SymbolicValue>(symbol-hash)
- val reset = WRef(`reset, UnknownType(), PortKind(), MALE)
for i in get-unique-keys(list(assign,resets)) do :
table[i] = match(get?(assign,i,false),get?(resets,i,false)) :
- (a:SymbolicValue,r:SymbolicValue) : SVMux(reset,r,a)
+ (a:SymbolicValue,r:SymbolicValue) : SVMux(rsignals[i],r,a)
(a:SymbolicValue,r:False) : a
- (a:False,r:SymbolicValue) : SVMux(reset,r,SVNul())
+ (a:False,r:SymbolicValue) : SVMux(rsignals[i],r,SVNul())
(a:False,r:False) : error("Shouldn't be here")
table
@@ -1280,12 +1280,17 @@ defn build-tables (s:Stmt,
assign:HashTable<Symbol,SymbolicValue>,
resets:HashTable<Symbol,SymbolicValue>,
flattn:HashTable<Symbol,True|False>,
+ rsignals:HashTable<Symbol,Expression>,
) -> False :
match(s) :
(s:DefWire) :
assign[name(s)] = SVNul()
flattn[name(s)] = true
- (s:DefRegister|DefAccessor) :
+ (s:DefRegister) :
+ assign[name(s)] = SVNul()
+ flattn[name(s)] = false
+ rsignals[name(s)] = reset(s)
+ (s:DefAccessor) :
assign[name(s)] = SVNul()
flattn[name(s)] = false
(s:DefInstance) : ;TODO only add instance input ports. This probably involves correcting instance genders
@@ -1316,8 +1321,8 @@ defn build-tables (s:Stmt,
val assign-a = deepcopy(assign)
val resets-c = deepcopy(resets)
val resets-a = deepcopy(resets)
- build-tables(conseq(s),assign-c,resets-c,flattn)
- build-tables(alt(s),assign-a,resets-a,flattn)
+ build-tables(conseq(s),assign-c,resets-c,flattn,rsignals)
+ build-tables(alt(s),assign-a,resets-a,flattn,rsignals)
for i in get-unique-keys(list(assign-c,assign-a)) do :
assign[i] = combine(flattn,assign-c,assign-a,i) as SymbolicValue
val r = combine(flattn,resets-c,resets-a,i)
@@ -1337,7 +1342,7 @@ defn build-tables (s:Stmt,
(e) : error("Shouldn't be here with ~" % [e])
if s typeof Connect : assign[key*] = SVExp(exp(s))
if s typeof OnReset : resets[key*] = SVExp(exp(s))
- (s:Begin) : for s* in body(s) do: build-tables(s*,assign,resets,flattn)
+ (s:Begin) : for s* in body(s) do: build-tables(s*,assign,resets,flattn,rsignals)
(s:DefMemory|DefNode|EmptyStmt) : false
;--------------- Expand Whens Pass -------------------
@@ -1413,13 +1418,14 @@ public defn expand-whens (c:Circuit) -> Circuit :
val assign = HashTable<Symbol,SymbolicValue>(symbol-hash)
val resets = HashTable<Symbol,SymbolicValue>(symbol-hash)
val flattn = HashTable<Symbol,True|False>(symbol-hash)
+ val rsignals = HashTable<Symbol,Expression>(symbol-hash)
for p in ports(m) do :
if direction(p) == OUTPUT :
assign[name(p)] = SVNul()
flattn[name(p)] = false
- build-tables(body(m),assign,resets,flattn)
+ build-tables(body(m),assign,resets,flattn,rsignals)
for x in assign do : assign[key(x)] = optimize(value(x))
for x in resets do : resets[key(x)] = optimize(value(x))
;val enables = get-enables(assign,kinds)
@@ -1430,7 +1436,7 @@ public defn expand-whens (c:Circuit) -> Circuit :
println-debug("====== Resets ======")
for x in resets do : println-debug(x)
- val table = merge-resets(assign,resets)
+ val table = merge-resets(assign,resets,rsignals)
println-debug("====== Table ======")
for x in table do : println-debug(x)
val decs = Vector<Stmt>()
@@ -1657,6 +1663,7 @@ public defn width! (t:Type) -> Width :
match(t) :
(t:UIntType) : width(t)
(t:SIntType) : width(t)
+ (t:ClockType) : IntWidth(1)
(t) : error("No width!")
public defn width! (e:Expression) -> Width : width!(type(e))
@@ -1664,10 +1671,10 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod
defn gen-constraints-s (s:Stmt) -> Stmt :
match(map(gen-constraints-s,s)) :
(s:DefWire) : DefWire(info(s),name(s),h[name(s)])
- (s:DefRegister) : DefRegister(info(s),name(s),h[name(s)])
+ (s:DefRegister) : DefRegister(info(s),name(s),h[name(s)],gen-constraints(clock(s)),gen-constraints(reset(s)))
(s:DefAccessor) : DefAccessor(info(s),name(s),gen-constraints(source(s)),gen-constraints(index(s)), acc-dir(s))
(s:DefInstance) : DefInstance(info(s),name(s),gen-constraints(module(s)))
- (s:DefMemory) : DefMemory(info(s),name(s),h[name(s)] as VectorType,seq?(s))
+ (s:DefMemory) : DefMemory(info(s),name(s),h[name(s)] as VectorType,seq?(s),gen-constraints(clock(s)))
(s:DefNode) :
val l = h[name(s)]
val r = gen-constraints(value(s))
@@ -1723,8 +1730,7 @@ defn build-environment (c:Circuit,m:Module,h:HashTable<Symbol,Type>) -> HashTabl
(s:DefRegister) : h[name(s)] = remove-unknowns(type(s))
(s:DefInstance) : h[name(s)] = h[name(module(s) as WRef)]
(s:DefMemory) : h[name(s)] = remove-unknowns(type(s))
- (s:DefAccessor) :
- h[name(s)] = remove-unknowns(type(type(source(s)) as VectorType))
+ (s:DefAccessor) : h[name(s)] = remove-unknowns(type(type(source(s)) as VectorType))
(s:DefNode) : h[name(s)] = remove-unknowns(type(value(s)))
(s) : false
do(build-environment,s)
@@ -1870,9 +1876,9 @@ defn inline-instances (c:Circuit) :
defn rename-s (s:Stmt,n:Symbol) -> Stmt :
map{rename-e{_,n},_} $ match(map(rename-s{_,n},s)) :
(s:DefWire) : DefWire(info(s),rename(name(s),n),type(s))
- (s:DefRegister) : DefRegister(info(s),rename(name(s),n),type(s))
+ (s:DefRegister) : DefRegister(info(s),rename(name(s),n),type(s),clock(s),reset(s))
(s:DefInstance) : error("Shouldn't be here")
- (s:DefMemory) : DefMemory(info(s),rename(name(s),n),type(s),seq?(s))
+ (s:DefMemory) : DefMemory(info(s),rename(name(s),n),type(s),seq?(s),clock(s))
(s:DefNode) : DefNode(info(s),rename(name(s),n),value(s))
(s) : s
for m in modules(c) do :
@@ -1901,11 +1907,17 @@ defn split-exp (c:Circuit) :
defn split-exp-e (e:Expression,n:Symbol|False,info:FileInfo) -> Expression :
match(map(split-exp-e{_,n,info},e)) :
(e:DoPrim) :
- val n* =
- if n typeof False : firrtl-gensym(`T,sh)
- else : firrtl-gensym(symbol-join([n as Symbol gen-delin]),sh)
- add(v,DefNode(info,n*,e))
- WRef(n*,type(e),NodeKind(),UNKNOWN-GENDER)
+ var all-same-type? = true
+ for x in args(e) do :
+ if type(x) != type(e) : all-same-type? = false
+ all-same-type? = false
+ if not all-same-type? :
+ val n* =
+ if n typeof False : firrtl-gensym(`T,sh)
+ else : firrtl-gensym(symbol-join([n as Symbol gen-delin]),sh)
+ add(v,DefNode(info,n*,e))
+ WRef(n*,type(e),NodeKind(),UNKNOWN-GENDER)
+ else : e
(e) : e
defn f (s:Stmt) -> False: split-exp-s(s,v,sh)
match(s) :
@@ -1916,25 +1928,24 @@ defn split-exp (c:Circuit) :
do(f,s)
(s:Connect) :
match(loc(s)) :
- ;(e:WritePort) : add(v,map(split-exp-e{_,full-name(exp(s)),info(s)},s))
(e) : add(v,map(split-exp-e{_,full-name(loc(s)),info(s)},s))
(s:DefNode) : add(v,map(split-exp-e{_,name(s),info(s)},s))
(s) : add(v,map(split-exp-e{_,false,info(s)},s))
false
- val start-time = current-time-us()
+ ;val start-time = current-time-us()
Circuit{info(c),_,main(c)} $
for m in modules(c) map :
match(m) :
(m:InModule) :
val v = Vector<Stmt>()
val sh = get-sym-hash(m)
- val before = current-time-us() - start-time
- println-all(["Before split: " before])
+ ;val before = current-time-us() - start-time
+ ;println-all(["Before split: " before])
split-exp-s(body(m),v,sh)
- val now = current-time-us() - start-time
- println-all(["After split: " now])
- println-all(["Diff: " now - before])
+ ;val now = current-time-us() - start-time
+ ;println-all(["After split: " now])
+ ;println-all(["Diff: " now - before])
InModule(info(m),name(m),ports(m),Begin(to-list(v)))
(m:ExModule) : m
@@ -2008,9 +2019,9 @@ public defn special-rename (original-sym:Symbol,new-sym:Symbol,c:Circuit) :
defn to-stmt (s:Stmt) -> Stmt :
map{to-type,_} $ match(map(to-exp,s)) :
(s:DefWire) : DefWire(info(s),rename(name(s)),type(s))
- (s:DefRegister) : DefRegister(info(s),rename(name(s)),type(s))
+ (s:DefRegister) : DefRegister(info(s),rename(name(s)),type(s),clock(s),reset(s))
(s:DefInstance) : DefInstance(info(s),rename(name(s)),module(s))
- (s:DefMemory) : DefMemory(info(s),rename(name(s)),type(s),seq?(s))
+ (s:DefMemory) : DefMemory(info(s),rename(name(s)),type(s),seq?(s),clock(s))
(s:DefNode) : DefNode(info(s),rename(name(s)),value(s))
(s:DefAccessor) : DefAccessor(info(s),rename(name(s)),source(s),index(s),acc-dir(s))
(s) : map(to-stmt,s)
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index 1904f92f..23591f45 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -36,6 +36,7 @@ defn get-width (t:Type) -> String :
match(t) :
(t:UIntType) : emit(width(t))
(t:SIntType) : emit(width(t))
+ (t:ClockType) : emit(IntWidth(1))
(t) : error("Non-supported type.")
defn remove-subfield (e:Expression) -> Expression :
@@ -140,8 +141,8 @@ defn get-name (e:Expression) -> Symbol :
(e) : error("Shouldn't be here")
defn emit-module (m:InModule) :
- val vdecs = Vector<KeyValue<Symbol,Stmt>>() ; all declarations
- val decs = HashTable<Symbol,Stmt>(symbol-hash) ; all declarations
+ val vdecs = Vector<KeyValue<Symbol,Stmt>>() ; all declarations in order, to preserve ordering
+ val decs = HashTable<Symbol,Stmt>(symbol-hash) ; all declarations, for fast lookups
val cons = HashTable<Symbol,Expression>(symbol-hash) ; all connections
val ens = HashTable<Symbol,Expression>(symbol-hash) ; all enables
defn build-table (m:InModule) :
@@ -166,7 +167,7 @@ defn emit-module (m:InModule) :
val regs = Vector<Streamable>()
val inits = Vector<Streamable>()
val assigns = Vector<Streamable>()
- val updates = Vector<Streamable>()
+ val updates = HashTable<Symbol,Vector<Streamable>>(symbol-hash)
val insts = HashTable<Symbol,Symbol>(symbol-hash) ; inst -> module
val inst-ports = HashTable<Symbol,Vector<Streamable>>(symbol-hash)
@@ -180,12 +181,14 @@ defn emit-module (m:InModule) :
add(assigns,["assign " sym " = " emit(cons[sym]) ";"])
(s:DefRegister) :
add(regs,["reg " get-width(type(s)) " " sym ";"])
+ val my-clk-update = get?(updates,get-name(clock(s)),Vector<Streamable>())
if key?(ens,sym) :
- add(updates,["if(" emit(ens[sym]) ") begin"])
- add(updates,[" " sym " <= " emit(cons[sym]) ";"])
- add(updates,["end"])
+ add(my-clk-update,["if(" emit(ens[sym]) ") begin"])
+ add(my-clk-update,[" " sym " <= " emit(cons[sym]) ";"])
+ add(my-clk-update,["end"])
else :
- add(updates,[sym " <= " emit(cons[sym]) ";"])
+ add(my-clk-update,[sym " <= " emit(cons[sym]) ";"])
+ updates[get-name(clock(s))] = my-clk-update
(s:DefMemory) :
val vtype = type(s) as VectorType
add(regs,["reg " get-width(type(vtype)) " " sym " [0:" size(vtype) "];"])
@@ -204,15 +207,17 @@ defn emit-module (m:InModule) :
if flip(f) == REVERSE :
add(assigns,["assign " n* " = " emit(cons[n*]) ";"])
(s:DefAccessor) :
+ val mem-declaration = decs[name(source(s) as Ref)] as DefMemory
switch {_ == acc-dir(s)} :
READ :
- val mem-declaration = decs[name(source(s) as Ref)]
- if seq?(mem-declaration as DefMemory) :
+ if seq?(mem-declaration) :
; to make it sequential, register the index for an additional cycle
val index* = Ref(firrtl-gensym(name(index(s) as Ref),sh),type(index(s)))
add(regs,[ "reg " get-width(type(index*)) " " name(index*) ";"])
add(inits,[name(index*) " = {" width!(type(index*)) "{$random}};"])
- add(updates,[name(index*) " <= " emit(index(s)) ";"])
+ val my-clk-update = get?(updates,get-name(clock(mem-declaration)),Vector<Streamable>())
+ add(my-clk-update,[name(index*) " <= " emit(index(s)) ";"])
+ updates[get-name(clock(mem-declaration))] = my-clk-update
; emit read accessor
add(wires,["wire " get-width(type(type(source(s)) as VectorType)) " " sym ";"])
@@ -222,27 +227,28 @@ defn emit-module (m:InModule) :
add(wires,["wire " get-width(type(type(source(s)) as VectorType)) " " sym ";"])
add(assigns,["assign " sym " = " emit(source(s)) "[" emit(index(s)) "];"])
WRITE :
+ val my-clk-update = get?(updates,get-name(clock(mem-declaration)),Vector<Streamable>())
if key?(ens,sym) :
- add(updates,["if(" emit(ens[sym]) ") begin"])
- add(updates,[" " emit(source(s)) "[" emit(index(s)) "] <= " emit(cons[sym]) ";"])
- add(updates,["end"])
+ add(my-clk-update,["if(" emit(ens[sym]) ") begin"])
+ add(my-clk-update,[" " emit(source(s)) "[" emit(index(s)) "] <= " emit(cons[sym]) ";"])
+ add(my-clk-update,["end"])
else :
- add(updates,[emit(source(s)) "[" emit(index(s)) "] <= " emit(cons[sym]) ";"])
+ add(my-clk-update,[emit(source(s)) "[" emit(index(s)) "] <= " emit(cons[sym]) ";"])
+ updates[get-name(clock(mem-declaration))] = my-clk-update
;==== Actually printing module =====
val port-indent = " "
- print-all(["module " name(m) "(input clk, input reset,\n"])
+ print-all(["module " name(m) "(\n"])
for (p in ports(m),i in 1 to false) do :
- if name(p) !=`reset :
- var end = ",\n"
- if length(ports(m)) - 1 == i :
- end = "\n);\n"
- switch {_ == direction(p)} :
- INPUT :
- print-all([port-indent "input " get-width(type(p)) " " name(p) end])
- OUTPUT :
- print-all([port-indent "output " get-width(type(p)) " " name(p) end])
- add(assigns,["assign " name(p) " = " emit(cons[name(p)]) ";"])
+ var end = ",\n"
+ if length(ports(m)) == i :
+ end = "\n);\n"
+ switch {_ == direction(p)} :
+ INPUT :
+ print-all([port-indent "input " get-width(type(p)) " " name(p) end])
+ OUTPUT :
+ print-all([port-indent "output " get-width(type(p)) " " name(p) end])
+ add(assigns,["assign " name(p) " = " emit(cons[name(p)]) ";"])
for w in wires do :
print(" ")
@@ -268,23 +274,22 @@ defn emit-module (m:InModule) :
for x in insts do :
println-all([" " value(x) " " key(x) " ("])
- print(" ")
- print-all([".clk( clk )"])
+ ;print-all([".clk( clk )"])
for (y in inst-ports[key(x)],i in 1 to false) do :
- print(",\n")
print(" ")
print-all(y)
- ;if length(inst-ports[key(x)]) != i :
- ;print(",\n")
+ if length(inst-ports[key(x)]) != i :
+ print(",\n")
println("\n );")
- if length(updates) != 0 :
- println(" always @(posedge clk) begin")
- for u in updates do :
- print(" ")
- println-all(u)
- println(" end")
-
+ for x in updates do :
+ if length(value(x)) != 0 :
+ println-all([" always @(posedge " key(x) ") begin"])
+ for u in value(x) do :
+ print(" ")
+ println-all(u)
+ println(" end")
+
println("endmodule")
diff --git a/test/chisel3/ALUTop.fir b/test/chisel3/ALUTop.fir
index a6fdfd95..df7235b7 100644
--- a/test/chisel3/ALUTop.fir
+++ b/test/chisel3/ALUTop.fir
@@ -1,5 +1,5 @@
; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
-;CHECK: Done!
+; CHECK: Done!
circuit ALUTop :
module ALU :
@@ -10,23 +10,23 @@ circuit ALUTop :
input alu_op : UInt<4>
node shamt = bits(B, 4, 0)
- node T_157 = add-wrap(A, B)
- node T_158 = sub-wrap(A, B)
- node T_159 = as-SInt(A)
+ node T_157 = addw(A, B)
+ node T_158 = subw(A, B)
+ node T_159 = asSInt(A)
node T_160 = dshr(T_159, shamt)
- node T_161 = as-UInt(T_160)
+ node T_161 = asUInt(T_160)
node T_162 = dshr(A, shamt)
node T_163 = dshl(A, shamt)
node T_164 = bits(T_163, 31, 0)
- node T_165 = convert(A)
- node T_166 = convert(B)
+ node T_165 = cvt(A)
+ node T_166 = cvt(B)
node T_167 = lt(T_165, T_166)
- node T_168 = as-UInt(T_167)
+ node T_168 = asUInt(T_167)
node T_169 = lt(A, B)
- node T_170 = as-UInt(T_169)
- node T_171 = bit-and(A, B)
- node T_172 = bit-or(A, B)
- node T_173 = bit-xor(A, B)
+ node T_170 = asUInt(T_169)
+ node T_171 = and(A, B)
+ node T_172 = or(A, B)
+ node T_173 = xor(A, B)
node T_174 = eq(UInt<4>(10), alu_op)
node T_175 = mux(T_174, A, B)
node T_176 = eq(UInt<4>(4), alu_op)
@@ -52,9 +52,9 @@ circuit ALUTop :
node T_195 = bits(oot, 31, 0)
out := T_195
node T_196 = bit(alu_op, 0)
- node T_197 = sub-wrap(UInt<1>(0), B)
+ node T_197 = subw(UInt<1>(0), B)
node T_198 = mux(T_196, T_197, B)
- node T_199 = add-wrap(A, T_198)
+ node T_199 = addw(A, T_198)
sum := T_199
module ALUdec :
input opcode : UInt<7>
diff --git a/test/chisel3/Control.fir b/test/chisel3/Control.fir
index 28bb3d87..08824c33 100644
--- a/test/chisel3/Control.fir
+++ b/test/chisel3/Control.fir
@@ -3,93 +3,95 @@
circuit Control :
module Control :
+ input clk : Clock
+ input reset : UInt<1>
output ctrl : {flip inst : UInt<32>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>, pc_sel : UInt<1>, inst_re : UInt<1>, flip stall : UInt<1>, data_re : UInt<1>, inst_type : UInt<1>, A_sel : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>}
- node T_831 = bit-and(UInt<7>(127), ctrl.inst)
+ node T_831 = and(UInt<7>(127), ctrl.inst)
node T_832 = eq(T_831, UInt<6>(55))
- node T_833 = bit-and(UInt<7>(127), ctrl.inst)
+ node T_833 = and(UInt<7>(127), ctrl.inst)
node T_834 = eq(T_833, UInt<5>(23))
- node T_835 = bit-and(UInt<7>(127), ctrl.inst)
+ node T_835 = and(UInt<7>(127), ctrl.inst)
node T_836 = eq(T_835, UInt<7>(111))
- node T_837 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_837 = and(UInt<15>(28799), ctrl.inst)
node T_838 = eq(T_837, UInt<7>(103))
- node T_839 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_839 = and(UInt<15>(28799), ctrl.inst)
node T_840 = eq(T_839, UInt<7>(99))
- node T_841 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_841 = and(UInt<15>(28799), ctrl.inst)
node T_842 = eq(T_841, UInt<13>(4195))
- node T_843 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_843 = and(UInt<15>(28799), ctrl.inst)
node T_844 = eq(T_843, UInt<15>(16483))
- node T_845 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_845 = and(UInt<15>(28799), ctrl.inst)
node T_846 = eq(T_845, UInt<15>(20579))
- node T_847 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_847 = and(UInt<15>(28799), ctrl.inst)
node T_848 = eq(T_847, UInt<15>(24675))
- node T_849 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_849 = and(UInt<15>(28799), ctrl.inst)
node T_850 = eq(T_849, UInt<15>(28771))
- node T_851 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_851 = and(UInt<15>(28799), ctrl.inst)
node T_852 = eq(T_851, UInt<2>(3))
- node T_853 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_853 = and(UInt<15>(28799), ctrl.inst)
node T_854 = eq(T_853, UInt<13>(4099))
- node T_855 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_855 = and(UInt<15>(28799), ctrl.inst)
node T_856 = eq(T_855, UInt<14>(8195))
- node T_857 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_857 = and(UInt<15>(28799), ctrl.inst)
node T_858 = eq(T_857, UInt<15>(16387))
- node T_859 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_859 = and(UInt<15>(28799), ctrl.inst)
node T_860 = eq(T_859, UInt<15>(20483))
- node T_861 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_861 = and(UInt<15>(28799), ctrl.inst)
node T_862 = eq(T_861, UInt<6>(35))
- node T_863 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_863 = and(UInt<15>(28799), ctrl.inst)
node T_864 = eq(T_863, UInt<13>(4131))
- node T_865 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_865 = and(UInt<15>(28799), ctrl.inst)
node T_866 = eq(T_865, UInt<14>(8227))
- node T_867 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_867 = and(UInt<15>(28799), ctrl.inst)
node T_868 = eq(T_867, UInt<5>(19))
- node T_869 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_869 = and(UInt<15>(28799), ctrl.inst)
node T_870 = eq(T_869, UInt<14>(8211))
- node T_871 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_871 = and(UInt<15>(28799), ctrl.inst)
node T_872 = eq(T_871, UInt<14>(12307))
- node T_873 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_873 = and(UInt<15>(28799), ctrl.inst)
node T_874 = eq(T_873, UInt<15>(16403))
- node T_875 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_875 = and(UInt<15>(28799), ctrl.inst)
node T_876 = eq(T_875, UInt<15>(24595))
- node T_877 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_877 = and(UInt<15>(28799), ctrl.inst)
node T_878 = eq(T_877, UInt<15>(28691))
- node T_879 = bit-and(UInt<32>(4261441663), ctrl.inst)
+ node T_879 = and(UInt<32>(4261441663), ctrl.inst)
node T_880 = eq(T_879, UInt<13>(4115))
- node T_881 = bit-and(UInt<32>(4261441663), ctrl.inst)
+ node T_881 = and(UInt<32>(4261441663), ctrl.inst)
node T_882 = eq(T_881, UInt<15>(20499))
- node T_883 = bit-and(UInt<32>(4261441663), ctrl.inst)
+ node T_883 = and(UInt<32>(4261441663), ctrl.inst)
node T_884 = eq(T_883, UInt<31>(1073762323))
- node T_885 = bit-and(UInt<32>(4261441663), ctrl.inst)
+ node T_885 = and(UInt<32>(4261441663), ctrl.inst)
node T_886 = eq(T_885, UInt<6>(51))
- node T_887 = bit-and(UInt<32>(4261441663), ctrl.inst)
+ node T_887 = and(UInt<32>(4261441663), ctrl.inst)
node T_888 = eq(T_887, UInt<31>(1073741875))
- node T_889 = bit-and(UInt<32>(4261441663), ctrl.inst)
+ node T_889 = and(UInt<32>(4261441663), ctrl.inst)
node T_890 = eq(T_889, UInt<13>(4147))
- node T_891 = bit-and(UInt<32>(4261441663), ctrl.inst)
+ node T_891 = and(UInt<32>(4261441663), ctrl.inst)
node T_892 = eq(T_891, UInt<14>(8243))
- node T_893 = bit-and(UInt<32>(4261441663), ctrl.inst)
+ node T_893 = and(UInt<32>(4261441663), ctrl.inst)
node T_894 = eq(T_893, UInt<14>(12339))
- node T_895 = bit-and(UInt<32>(4261441663), ctrl.inst)
+ node T_895 = and(UInt<32>(4261441663), ctrl.inst)
node T_896 = eq(T_895, UInt<15>(16435))
- node T_897 = bit-and(UInt<32>(4261441663), ctrl.inst)
+ node T_897 = and(UInt<32>(4261441663), ctrl.inst)
node T_898 = eq(T_897, UInt<15>(20531))
- node T_899 = bit-and(UInt<32>(4261441663), ctrl.inst)
+ node T_899 = and(UInt<32>(4261441663), ctrl.inst)
node T_900 = eq(T_899, UInt<31>(1073762355))
- node T_901 = bit-and(UInt<32>(4261441663), ctrl.inst)
+ node T_901 = and(UInt<32>(4261441663), ctrl.inst)
node T_902 = eq(T_901, UInt<15>(24627))
- node T_903 = bit-and(UInt<32>(4261441663), ctrl.inst)
+ node T_903 = and(UInt<32>(4261441663), ctrl.inst)
node T_904 = eq(T_903, UInt<15>(28723))
- node T_905 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_905 = and(UInt<15>(28799), ctrl.inst)
node T_906 = eq(T_905, UInt<13>(4211))
- node T_907 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_907 = and(UInt<15>(28799), ctrl.inst)
node T_908 = eq(T_907, UInt<14>(8307))
- node T_909 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_909 = and(UInt<15>(28799), ctrl.inst)
node T_910 = eq(T_909, UInt<14>(12403))
- node T_911 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_911 = and(UInt<15>(28799), ctrl.inst)
node T_912 = eq(T_911, UInt<15>(20595))
- node T_913 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_913 = and(UInt<15>(28799), ctrl.inst)
node T_914 = eq(T_913, UInt<15>(24691))
- node T_915 = bit-and(UInt<15>(28799), ctrl.inst)
+ node T_915 = and(UInt<15>(28799), ctrl.inst)
node T_916 = eq(T_915, UInt<15>(28787))
node T_917 = mux(T_916, UInt<1>(0), UInt<1>(0))
node T_918 = mux(T_914, UInt<1>(0), T_917)
@@ -609,20 +611,20 @@ circuit Control :
node T_1432 = mux(T_832, UInt<2>(0), T_1431)
node rs1_addr = bits(ctrl.inst, 19, 15)
node rs2_addr = bits(ctrl.inst, 24, 20)
- reg st_type : UInt<2>
- reg ld_type : UInt<3>
- reg wb_sel : UInt<2>
+ reg st_type : UInt<2>, clk, reset
+ reg ld_type : UInt<3>, clk, reset
+ reg wb_sel : UInt<2>, clk, reset
node T_1433 = bit(T_1389, 0)
- reg wb_en : UInt<1>
- reg csr_cmd : UInt<2>
+ reg wb_en : UInt<1>, clk, reset
+ reg csr_cmd : UInt<2>, clk, reset
ctrl.pc_sel := T_959
- node T_1434 = bit-not(ctrl.stall)
- node T_1435 = bit-not(ctrl.data_re)
- node T_1436 = bit-and(T_1434, T_1435)
+ node T_1434 = not(ctrl.stall)
+ node T_1435 = not(ctrl.data_re)
+ node T_1436 = and(T_1434, T_1435)
ctrl.inst_re := T_1436
node T_1437 = neq(T_1303, UInt<3>(7))
node T_1438 = bit(T_1217, 0)
- node T_1439 = bit-or(T_1437, T_1438)
+ node T_1439 = or(T_1437, T_1438)
node T_1440 = mux(T_1439, UInt<1>(1), UInt<1>(0))
ctrl.inst_type := T_1440
ctrl.A_sel := T_1002
@@ -631,7 +633,7 @@ circuit Control :
ctrl.alu_op := T_1131
ctrl.br_type := T_1174
ctrl.st_type := T_1260
- node T_1441 = bit-not(ctrl.stall)
+ node T_1441 = not(ctrl.stall)
when T_1441 :
st_type := ctrl.st_type
ld_type := T_1303
diff --git a/test/chisel3/Core.fir b/test/chisel3/Core.fir
index e9aef65f..7e87bb07 100644
--- a/test/chisel3/Core.fir
+++ b/test/chisel3/Core.fir
@@ -364,646 +364,648 @@ circuit Core :
regFile.waddr := ex_rd_addr
regFile.wdata := regWrite
module Control :
- output ctrl : {flip inst : UInt<32>, flip stall : UInt<1>, pc_sel : UInt<1>, inst_re : UInt<1>, inst_type : UInt<1>, A_sel : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>, data_re : UInt<1>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>}
+ input clk : Clock
+ input reset : UInt<1>
+ output ctrl : {flip inst : UInt<32>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>, pc_sel : UInt<1>, inst_re : UInt<1>, flip stall : UInt<1>, data_re : UInt<1>, inst_type : UInt<1>, A_sel : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>}
- node T_1436 = bit-and(UInt<7>(127), ctrl.inst)
- node T_1437 = eq(T_1436, UInt<6>(55))
- node T_1438 = bit-and(UInt<7>(127), ctrl.inst)
- node T_1439 = eq(T_1438, UInt<5>(23))
- node T_1440 = bit-and(UInt<7>(127), ctrl.inst)
- node T_1441 = eq(T_1440, UInt<7>(111))
- node T_1442 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1443 = eq(T_1442, UInt<7>(103))
- node T_1444 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1445 = eq(T_1444, UInt<7>(99))
- node T_1446 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1447 = eq(T_1446, UInt<13>(4195))
- node T_1448 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1449 = eq(T_1448, UInt<15>(16483))
- node T_1450 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1451 = eq(T_1450, UInt<15>(20579))
- node T_1452 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1453 = eq(T_1452, UInt<15>(24675))
- node T_1454 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1455 = eq(T_1454, UInt<15>(28771))
- node T_1456 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1457 = eq(T_1456, UInt<2>(3))
- node T_1458 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1459 = eq(T_1458, UInt<13>(4099))
- node T_1460 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1461 = eq(T_1460, UInt<14>(8195))
- node T_1462 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1463 = eq(T_1462, UInt<15>(16387))
- node T_1464 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1465 = eq(T_1464, UInt<15>(20483))
- node T_1466 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1467 = eq(T_1466, UInt<6>(35))
- node T_1468 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1469 = eq(T_1468, UInt<13>(4131))
- node T_1470 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1471 = eq(T_1470, UInt<14>(8227))
- node T_1472 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1473 = eq(T_1472, UInt<5>(19))
- node T_1474 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1475 = eq(T_1474, UInt<14>(8211))
- node T_1476 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1477 = eq(T_1476, UInt<14>(12307))
- node T_1478 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1479 = eq(T_1478, UInt<15>(16403))
- node T_1480 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1481 = eq(T_1480, UInt<15>(24595))
- node T_1482 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1483 = eq(T_1482, UInt<15>(28691))
- node T_1484 = bit-and(UInt<32>(4261441663), ctrl.inst)
- node T_1485 = eq(T_1484, UInt<13>(4115))
- node T_1486 = bit-and(UInt<32>(4261441663), ctrl.inst)
- node T_1487 = eq(T_1486, UInt<15>(20499))
- node T_1488 = bit-and(UInt<32>(4261441663), ctrl.inst)
- node T_1489 = eq(T_1488, UInt<31>(1073762323))
- node T_1490 = bit-and(UInt<32>(4261441663), ctrl.inst)
- node T_1491 = eq(T_1490, UInt<6>(51))
- node T_1492 = bit-and(UInt<32>(4261441663), ctrl.inst)
- node T_1493 = eq(T_1492, UInt<31>(1073741875))
- node T_1494 = bit-and(UInt<32>(4261441663), ctrl.inst)
- node T_1495 = eq(T_1494, UInt<13>(4147))
- node T_1496 = bit-and(UInt<32>(4261441663), ctrl.inst)
- node T_1497 = eq(T_1496, UInt<14>(8243))
- node T_1498 = bit-and(UInt<32>(4261441663), ctrl.inst)
- node T_1499 = eq(T_1498, UInt<14>(12339))
- node T_1500 = bit-and(UInt<32>(4261441663), ctrl.inst)
- node T_1501 = eq(T_1500, UInt<15>(16435))
- node T_1502 = bit-and(UInt<32>(4261441663), ctrl.inst)
- node T_1503 = eq(T_1502, UInt<15>(20531))
- node T_1504 = bit-and(UInt<32>(4261441663), ctrl.inst)
- node T_1505 = eq(T_1504, UInt<31>(1073762355))
- node T_1506 = bit-and(UInt<32>(4261441663), ctrl.inst)
- node T_1507 = eq(T_1506, UInt<15>(24627))
- node T_1508 = bit-and(UInt<32>(4261441663), ctrl.inst)
- node T_1509 = eq(T_1508, UInt<15>(28723))
- node T_1510 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1511 = eq(T_1510, UInt<13>(4211))
- node T_1512 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1513 = eq(T_1512, UInt<14>(8307))
- node T_1514 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1515 = eq(T_1514, UInt<14>(12403))
- node T_1516 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1517 = eq(T_1516, UInt<15>(20595))
- node T_1518 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1519 = eq(T_1518, UInt<15>(24691))
- node T_1520 = bit-and(UInt<15>(28799), ctrl.inst)
- node T_1521 = eq(T_1520, UInt<15>(28787))
- node T_1522 = mux(T_1521, UInt<1>(0), UInt<1>(0))
- node T_1523 = mux(T_1519, UInt<1>(0), T_1522)
- node T_1524 = mux(T_1517, UInt<1>(0), T_1523)
- node T_1525 = mux(T_1515, UInt<1>(0), T_1524)
- node T_1526 = mux(T_1513, UInt<1>(0), T_1525)
- node T_1527 = mux(T_1511, UInt<1>(0), T_1526)
- node T_1528 = mux(T_1509, UInt<1>(0), T_1527)
- node T_1529 = mux(T_1507, UInt<1>(0), T_1528)
- node T_1530 = mux(T_1505, UInt<1>(0), T_1529)
- node T_1531 = mux(T_1503, UInt<1>(0), T_1530)
- node T_1532 = mux(T_1501, UInt<1>(0), T_1531)
- node T_1533 = mux(T_1499, UInt<1>(0), T_1532)
- node T_1534 = mux(T_1497, UInt<1>(0), T_1533)
- node T_1535 = mux(T_1495, UInt<1>(0), T_1534)
- node T_1536 = mux(T_1493, UInt<1>(0), T_1535)
- node T_1537 = mux(T_1491, UInt<1>(0), T_1536)
- node T_1538 = mux(T_1489, UInt<1>(0), T_1537)
- node T_1539 = mux(T_1487, UInt<1>(0), T_1538)
- node T_1540 = mux(T_1485, UInt<1>(0), T_1539)
- node T_1541 = mux(T_1483, UInt<1>(0), T_1540)
- node T_1542 = mux(T_1481, UInt<1>(0), T_1541)
- node T_1543 = mux(T_1479, UInt<1>(0), T_1542)
- node T_1544 = mux(T_1477, UInt<1>(0), T_1543)
- node T_1545 = mux(T_1475, UInt<1>(0), T_1544)
- node T_1546 = mux(T_1473, UInt<1>(0), T_1545)
- node T_1547 = mux(T_1471, UInt<1>(0), T_1546)
- node T_1548 = mux(T_1469, UInt<1>(0), T_1547)
- node T_1549 = mux(T_1467, UInt<1>(0), T_1548)
- node T_1550 = mux(T_1465, UInt<1>(0), T_1549)
- node T_1551 = mux(T_1463, UInt<1>(0), T_1550)
- node T_1552 = mux(T_1461, UInt<1>(0), T_1551)
- node T_1553 = mux(T_1459, UInt<1>(0), T_1552)
- node T_1554 = mux(T_1457, UInt<1>(0), T_1553)
- node T_1555 = mux(T_1455, UInt<1>(0), T_1554)
- node T_1556 = mux(T_1453, UInt<1>(0), T_1555)
- node T_1557 = mux(T_1451, UInt<1>(0), T_1556)
- node T_1558 = mux(T_1449, UInt<1>(0), T_1557)
- node T_1559 = mux(T_1447, UInt<1>(0), T_1558)
- node T_1560 = mux(T_1445, UInt<1>(0), T_1559)
- node T_1561 = mux(T_1443, UInt<1>(1), T_1560)
- node T_1562 = mux(T_1441, UInt<1>(1), T_1561)
- node T_1563 = mux(T_1439, UInt<1>(0), T_1562)
- node T_1564 = mux(T_1437, UInt<1>(0), T_1563)
- node T_1565 = mux(T_1521, UInt<1>(1), UInt<1>(1))
- node T_1566 = mux(T_1519, UInt<1>(1), T_1565)
- node T_1567 = mux(T_1517, UInt<1>(1), T_1566)
- node T_1568 = mux(T_1515, UInt<1>(0), T_1567)
- node T_1569 = mux(T_1513, UInt<1>(0), T_1568)
- node T_1570 = mux(T_1511, UInt<1>(0), T_1569)
- node T_1571 = mux(T_1509, UInt<1>(0), T_1570)
- node T_1572 = mux(T_1507, UInt<1>(0), T_1571)
- node T_1573 = mux(T_1505, UInt<1>(0), T_1572)
- node T_1574 = mux(T_1503, UInt<1>(0), T_1573)
- node T_1575 = mux(T_1501, UInt<1>(0), T_1574)
- node T_1576 = mux(T_1499, UInt<1>(0), T_1575)
- node T_1577 = mux(T_1497, UInt<1>(0), T_1576)
- node T_1578 = mux(T_1495, UInt<1>(0), T_1577)
- node T_1579 = mux(T_1493, UInt<1>(0), T_1578)
- node T_1580 = mux(T_1491, UInt<1>(0), T_1579)
- node T_1581 = mux(T_1489, UInt<1>(0), T_1580)
- node T_1582 = mux(T_1487, UInt<1>(0), T_1581)
- node T_1583 = mux(T_1485, UInt<1>(0), T_1582)
- node T_1584 = mux(T_1483, UInt<1>(0), T_1583)
- node T_1585 = mux(T_1481, UInt<1>(0), T_1584)
- node T_1586 = mux(T_1479, UInt<1>(0), T_1585)
- node T_1587 = mux(T_1477, UInt<1>(0), T_1586)
- node T_1588 = mux(T_1475, UInt<1>(0), T_1587)
- node T_1589 = mux(T_1473, UInt<1>(0), T_1588)
- node T_1590 = mux(T_1471, UInt<1>(0), T_1589)
- node T_1591 = mux(T_1469, UInt<1>(0), T_1590)
- node T_1592 = mux(T_1467, UInt<1>(0), T_1591)
- node T_1593 = mux(T_1465, UInt<1>(0), T_1592)
- node T_1594 = mux(T_1463, UInt<1>(0), T_1593)
- node T_1595 = mux(T_1461, UInt<1>(0), T_1594)
- node T_1596 = mux(T_1459, UInt<1>(0), T_1595)
- node T_1597 = mux(T_1457, UInt<1>(0), T_1596)
- node T_1598 = mux(T_1455, UInt<1>(1), T_1597)
- node T_1599 = mux(T_1453, UInt<1>(1), T_1598)
- node T_1600 = mux(T_1451, UInt<1>(1), T_1599)
- node T_1601 = mux(T_1449, UInt<1>(1), T_1600)
- node T_1602 = mux(T_1447, UInt<1>(1), T_1601)
- node T_1603 = mux(T_1445, UInt<1>(1), T_1602)
- node T_1604 = mux(T_1443, UInt<1>(0), T_1603)
- node T_1605 = mux(T_1441, UInt<1>(1), T_1604)
- node T_1606 = mux(T_1439, UInt<1>(1), T_1605)
- node T_1607 = mux(T_1437, UInt<1>(1), T_1606)
- node T_1608 = mux(T_1521, UInt<1>(1), UInt<1>(0))
- node T_1609 = mux(T_1519, UInt<1>(1), T_1608)
- node T_1610 = mux(T_1517, UInt<1>(1), T_1609)
- node T_1611 = mux(T_1515, UInt<1>(0), T_1610)
- node T_1612 = mux(T_1513, UInt<1>(0), T_1611)
- node T_1613 = mux(T_1511, UInt<1>(0), T_1612)
- node T_1614 = mux(T_1509, UInt<1>(0), T_1613)
- node T_1615 = mux(T_1507, UInt<1>(0), T_1614)
- node T_1616 = mux(T_1505, UInt<1>(0), T_1615)
- node T_1617 = mux(T_1503, UInt<1>(0), T_1616)
- node T_1618 = mux(T_1501, UInt<1>(0), T_1617)
- node T_1619 = mux(T_1499, UInt<1>(0), T_1618)
- node T_1620 = mux(T_1497, UInt<1>(0), T_1619)
- node T_1621 = mux(T_1495, UInt<1>(0), T_1620)
- node T_1622 = mux(T_1493, UInt<1>(0), T_1621)
- node T_1623 = mux(T_1491, UInt<1>(0), T_1622)
- node T_1624 = mux(T_1489, UInt<1>(1), T_1623)
- node T_1625 = mux(T_1487, UInt<1>(1), T_1624)
- node T_1626 = mux(T_1485, UInt<1>(1), T_1625)
- node T_1627 = mux(T_1483, UInt<1>(1), T_1626)
- node T_1628 = mux(T_1481, UInt<1>(1), T_1627)
- node T_1629 = mux(T_1479, UInt<1>(1), T_1628)
- node T_1630 = mux(T_1477, UInt<1>(1), T_1629)
- node T_1631 = mux(T_1475, UInt<1>(1), T_1630)
- node T_1632 = mux(T_1473, UInt<1>(1), T_1631)
- node T_1633 = mux(T_1471, UInt<1>(1), T_1632)
- node T_1634 = mux(T_1469, UInt<1>(1), T_1633)
- node T_1635 = mux(T_1467, UInt<1>(1), T_1634)
- node T_1636 = mux(T_1465, UInt<1>(1), T_1635)
- node T_1637 = mux(T_1463, UInt<1>(1), T_1636)
- node T_1638 = mux(T_1461, UInt<1>(1), T_1637)
- node T_1639 = mux(T_1459, UInt<1>(1), T_1638)
- node T_1640 = mux(T_1457, UInt<1>(1), T_1639)
- node T_1641 = mux(T_1455, UInt<1>(1), T_1640)
- node T_1642 = mux(T_1453, UInt<1>(1), T_1641)
- node T_1643 = mux(T_1451, UInt<1>(1), T_1642)
- node T_1644 = mux(T_1449, UInt<1>(1), T_1643)
- node T_1645 = mux(T_1447, UInt<1>(1), T_1644)
- node T_1646 = mux(T_1445, UInt<1>(1), T_1645)
- node T_1647 = mux(T_1443, UInt<1>(1), T_1646)
- node T_1648 = mux(T_1441, UInt<1>(1), T_1647)
- node T_1649 = mux(T_1439, UInt<1>(1), T_1648)
- node T_1650 = mux(T_1437, UInt<1>(1), T_1649)
- node T_1651 = mux(T_1521, UInt<3>(5), UInt<3>(7))
- node T_1652 = mux(T_1519, UInt<3>(5), T_1651)
- node T_1653 = mux(T_1517, UInt<3>(5), T_1652)
- node T_1654 = mux(T_1515, UInt<3>(5), T_1653)
- node T_1655 = mux(T_1513, UInt<3>(5), T_1654)
- node T_1656 = mux(T_1511, UInt<3>(5), T_1655)
- node T_1657 = mux(T_1509, UInt<3>(7), T_1656)
- node T_1658 = mux(T_1507, UInt<3>(7), T_1657)
- node T_1659 = mux(T_1505, UInt<3>(7), T_1658)
- node T_1660 = mux(T_1503, UInt<3>(7), T_1659)
- node T_1661 = mux(T_1501, UInt<3>(7), T_1660)
- node T_1662 = mux(T_1499, UInt<3>(7), T_1661)
- node T_1663 = mux(T_1497, UInt<3>(7), T_1662)
- node T_1664 = mux(T_1495, UInt<3>(7), T_1663)
- node T_1665 = mux(T_1493, UInt<3>(7), T_1664)
- node T_1666 = mux(T_1491, UInt<3>(7), T_1665)
- node T_1667 = mux(T_1489, UInt<3>(0), T_1666)
- node T_1668 = mux(T_1487, UInt<3>(0), T_1667)
- node T_1669 = mux(T_1485, UInt<3>(0), T_1668)
- node T_1670 = mux(T_1483, UInt<3>(0), T_1669)
- node T_1671 = mux(T_1481, UInt<3>(0), T_1670)
- node T_1672 = mux(T_1479, UInt<3>(0), T_1671)
- node T_1673 = mux(T_1477, UInt<3>(0), T_1672)
- node T_1674 = mux(T_1475, UInt<3>(0), T_1673)
- node T_1675 = mux(T_1473, UInt<3>(0), T_1674)
- node T_1676 = mux(T_1471, UInt<3>(1), T_1675)
- node T_1677 = mux(T_1469, UInt<3>(1), T_1676)
- node T_1678 = mux(T_1467, UInt<3>(1), T_1677)
- node T_1679 = mux(T_1465, UInt<3>(0), T_1678)
- node T_1680 = mux(T_1463, UInt<3>(0), T_1679)
- node T_1681 = mux(T_1461, UInt<3>(0), T_1680)
- node T_1682 = mux(T_1459, UInt<3>(0), T_1681)
- node T_1683 = mux(T_1457, UInt<3>(0), T_1682)
- node T_1684 = mux(T_1455, UInt<3>(4), T_1683)
- node T_1685 = mux(T_1453, UInt<3>(4), T_1684)
- node T_1686 = mux(T_1451, UInt<3>(4), T_1685)
- node T_1687 = mux(T_1449, UInt<3>(4), T_1686)
- node T_1688 = mux(T_1447, UInt<3>(4), T_1687)
- node T_1689 = mux(T_1445, UInt<3>(4), T_1688)
- node T_1690 = mux(T_1443, UInt<3>(0), T_1689)
- node T_1691 = mux(T_1441, UInt<3>(3), T_1690)
- node T_1692 = mux(T_1439, UInt<3>(2), T_1691)
- node T_1693 = mux(T_1437, UInt<3>(2), T_1692)
- node T_1694 = mux(T_1521, UInt<4>(11), UInt<4>(15))
- node T_1695 = mux(T_1519, UInt<4>(11), T_1694)
- node T_1696 = mux(T_1517, UInt<4>(11), T_1695)
- node T_1697 = mux(T_1515, UInt<4>(10), T_1696)
- node T_1698 = mux(T_1513, UInt<4>(10), T_1697)
- node T_1699 = mux(T_1511, UInt<4>(10), T_1698)
- node T_1700 = mux(T_1509, UInt<4>(2), T_1699)
- node T_1701 = mux(T_1507, UInt<4>(3), T_1700)
- node T_1702 = mux(T_1505, UInt<4>(9), T_1701)
- node T_1703 = mux(T_1503, UInt<4>(8), T_1702)
- node T_1704 = mux(T_1501, UInt<4>(4), T_1703)
- node T_1705 = mux(T_1499, UInt<4>(7), T_1704)
- node T_1706 = mux(T_1497, UInt<4>(5), T_1705)
- node T_1707 = mux(T_1495, UInt<4>(6), T_1706)
- node T_1708 = mux(T_1493, UInt<4>(1), T_1707)
- node T_1709 = mux(T_1491, UInt<4>(0), T_1708)
- node T_1710 = mux(T_1489, UInt<4>(9), T_1709)
- node T_1711 = mux(T_1487, UInt<4>(8), T_1710)
- node T_1712 = mux(T_1485, UInt<4>(6), T_1711)
- node T_1713 = mux(T_1483, UInt<4>(2), T_1712)
- node T_1714 = mux(T_1481, UInt<4>(3), T_1713)
- node T_1715 = mux(T_1479, UInt<4>(4), T_1714)
- node T_1716 = mux(T_1477, UInt<4>(7), T_1715)
- node T_1717 = mux(T_1475, UInt<4>(5), T_1716)
- node T_1718 = mux(T_1473, UInt<4>(0), T_1717)
- node T_1719 = mux(T_1471, UInt<4>(0), T_1718)
- node T_1720 = mux(T_1469, UInt<4>(0), T_1719)
- node T_1721 = mux(T_1467, UInt<4>(0), T_1720)
- node T_1722 = mux(T_1465, UInt<4>(0), T_1721)
- node T_1723 = mux(T_1463, UInt<4>(0), T_1722)
- node T_1724 = mux(T_1461, UInt<4>(0), T_1723)
- node T_1725 = mux(T_1459, UInt<4>(0), T_1724)
- node T_1726 = mux(T_1457, UInt<4>(0), T_1725)
- node T_1727 = mux(T_1455, UInt<4>(0), T_1726)
- node T_1728 = mux(T_1453, UInt<4>(0), T_1727)
- node T_1729 = mux(T_1451, UInt<4>(0), T_1728)
- node T_1730 = mux(T_1449, UInt<4>(0), T_1729)
- node T_1731 = mux(T_1447, UInt<4>(0), T_1730)
- node T_1732 = mux(T_1445, UInt<4>(0), T_1731)
- node T_1733 = mux(T_1443, UInt<4>(0), T_1732)
- node T_1734 = mux(T_1441, UInt<4>(0), T_1733)
- node T_1735 = mux(T_1439, UInt<4>(0), T_1734)
- node T_1736 = mux(T_1437, UInt<4>(11), T_1735)
- node T_1737 = mux(T_1521, UInt<3>(7), UInt<3>(7))
- node T_1738 = mux(T_1519, UInt<3>(7), T_1737)
- node T_1739 = mux(T_1517, UInt<3>(7), T_1738)
- node T_1740 = mux(T_1515, UInt<3>(7), T_1739)
- node T_1741 = mux(T_1513, UInt<3>(7), T_1740)
- node T_1742 = mux(T_1511, UInt<3>(7), T_1741)
- node T_1743 = mux(T_1509, UInt<3>(7), T_1742)
- node T_1744 = mux(T_1507, UInt<3>(7), T_1743)
- node T_1745 = mux(T_1505, UInt<3>(7), T_1744)
- node T_1746 = mux(T_1503, UInt<3>(7), T_1745)
- node T_1747 = mux(T_1501, UInt<3>(7), T_1746)
- node T_1748 = mux(T_1499, UInt<3>(7), T_1747)
- node T_1749 = mux(T_1497, UInt<3>(7), T_1748)
- node T_1750 = mux(T_1495, UInt<3>(7), T_1749)
- node T_1751 = mux(T_1493, UInt<3>(7), T_1750)
- node T_1752 = mux(T_1491, UInt<3>(7), T_1751)
- node T_1753 = mux(T_1489, UInt<3>(7), T_1752)
- node T_1754 = mux(T_1487, UInt<3>(7), T_1753)
- node T_1755 = mux(T_1485, UInt<3>(7), T_1754)
- node T_1756 = mux(T_1483, UInt<3>(7), T_1755)
- node T_1757 = mux(T_1481, UInt<3>(7), T_1756)
- node T_1758 = mux(T_1479, UInt<3>(7), T_1757)
- node T_1759 = mux(T_1477, UInt<3>(7), T_1758)
- node T_1760 = mux(T_1475, UInt<3>(7), T_1759)
- node T_1761 = mux(T_1473, UInt<3>(7), T_1760)
- node T_1762 = mux(T_1471, UInt<3>(7), T_1761)
- node T_1763 = mux(T_1469, UInt<3>(7), T_1762)
- node T_1764 = mux(T_1467, UInt<3>(7), T_1763)
- node T_1765 = mux(T_1465, UInt<3>(7), T_1764)
- node T_1766 = mux(T_1463, UInt<3>(7), T_1765)
- node T_1767 = mux(T_1461, UInt<3>(7), T_1766)
- node T_1768 = mux(T_1459, UInt<3>(7), T_1767)
- node T_1769 = mux(T_1457, UInt<3>(7), T_1768)
- node T_1770 = mux(T_1455, UInt<3>(4), T_1769)
- node T_1771 = mux(T_1453, UInt<3>(0), T_1770)
- node T_1772 = mux(T_1451, UInt<3>(5), T_1771)
- node T_1773 = mux(T_1449, UInt<3>(1), T_1772)
- node T_1774 = mux(T_1447, UInt<3>(6), T_1773)
- node T_1775 = mux(T_1445, UInt<3>(2), T_1774)
- node T_1776 = mux(T_1443, UInt<3>(7), T_1775)
- node T_1777 = mux(T_1441, UInt<3>(7), T_1776)
- node T_1778 = mux(T_1439, UInt<3>(7), T_1777)
- node T_1779 = mux(T_1437, UInt<3>(7), T_1778)
- node T_1780 = mux(T_1521, UInt<1>(0), UInt<1>(0))
- node T_1781 = mux(T_1519, UInt<1>(0), T_1780)
- node T_1782 = mux(T_1517, UInt<1>(0), T_1781)
- node T_1783 = mux(T_1515, UInt<1>(0), T_1782)
- node T_1784 = mux(T_1513, UInt<1>(0), T_1783)
- node T_1785 = mux(T_1511, UInt<1>(0), T_1784)
- node T_1786 = mux(T_1509, UInt<1>(0), T_1785)
- node T_1787 = mux(T_1507, UInt<1>(0), T_1786)
- node T_1788 = mux(T_1505, UInt<1>(0), T_1787)
- node T_1789 = mux(T_1503, UInt<1>(0), T_1788)
- node T_1790 = mux(T_1501, UInt<1>(0), T_1789)
- node T_1791 = mux(T_1499, UInt<1>(0), T_1790)
- node T_1792 = mux(T_1497, UInt<1>(0), T_1791)
- node T_1793 = mux(T_1495, UInt<1>(0), T_1792)
- node T_1794 = mux(T_1493, UInt<1>(0), T_1793)
- node T_1795 = mux(T_1491, UInt<1>(0), T_1794)
- node T_1796 = mux(T_1489, UInt<1>(0), T_1795)
- node T_1797 = mux(T_1487, UInt<1>(0), T_1796)
- node T_1798 = mux(T_1485, UInt<1>(0), T_1797)
- node T_1799 = mux(T_1483, UInt<1>(0), T_1798)
- node T_1800 = mux(T_1481, UInt<1>(0), T_1799)
- node T_1801 = mux(T_1479, UInt<1>(0), T_1800)
- node T_1802 = mux(T_1477, UInt<1>(0), T_1801)
- node T_1803 = mux(T_1475, UInt<1>(0), T_1802)
- node T_1804 = mux(T_1473, UInt<1>(0), T_1803)
- node T_1805 = mux(T_1471, UInt<1>(0), T_1804)
- node T_1806 = mux(T_1469, UInt<1>(0), T_1805)
- node T_1807 = mux(T_1467, UInt<1>(0), T_1806)
- node T_1808 = mux(T_1465, UInt<1>(0), T_1807)
- node T_1809 = mux(T_1463, UInt<1>(0), T_1808)
- node T_1810 = mux(T_1461, UInt<1>(0), T_1809)
- node T_1811 = mux(T_1459, UInt<1>(0), T_1810)
- node T_1812 = mux(T_1457, UInt<1>(0), T_1811)
- node T_1813 = mux(T_1455, UInt<1>(0), T_1812)
- node T_1814 = mux(T_1453, UInt<1>(0), T_1813)
- node T_1815 = mux(T_1451, UInt<1>(0), T_1814)
- node T_1816 = mux(T_1449, UInt<1>(0), T_1815)
- node T_1817 = mux(T_1447, UInt<1>(0), T_1816)
- node T_1818 = mux(T_1445, UInt<1>(0), T_1817)
- node T_1819 = mux(T_1443, UInt<1>(1), T_1818)
- node T_1820 = mux(T_1441, UInt<1>(1), T_1819)
- node T_1821 = mux(T_1439, UInt<1>(0), T_1820)
- node T_1822 = mux(T_1437, UInt<1>(0), T_1821)
- node T_1823 = mux(T_1521, UInt<2>(3), UInt<2>(3))
- node T_1824 = mux(T_1519, UInt<2>(3), T_1823)
- node T_1825 = mux(T_1517, UInt<2>(3), T_1824)
- node T_1826 = mux(T_1515, UInt<2>(3), T_1825)
- node T_1827 = mux(T_1513, UInt<2>(3), T_1826)
- node T_1828 = mux(T_1511, UInt<2>(3), T_1827)
- node T_1829 = mux(T_1509, UInt<2>(3), T_1828)
- node T_1830 = mux(T_1507, UInt<2>(3), T_1829)
- node T_1831 = mux(T_1505, UInt<2>(3), T_1830)
- node T_1832 = mux(T_1503, UInt<2>(3), T_1831)
- node T_1833 = mux(T_1501, UInt<2>(3), T_1832)
- node T_1834 = mux(T_1499, UInt<2>(3), T_1833)
- node T_1835 = mux(T_1497, UInt<2>(3), T_1834)
- node T_1836 = mux(T_1495, UInt<2>(3), T_1835)
- node T_1837 = mux(T_1493, UInt<2>(3), T_1836)
- node T_1838 = mux(T_1491, UInt<2>(3), T_1837)
- node T_1839 = mux(T_1489, UInt<2>(3), T_1838)
- node T_1840 = mux(T_1487, UInt<2>(3), T_1839)
- node T_1841 = mux(T_1485, UInt<2>(3), T_1840)
- node T_1842 = mux(T_1483, UInt<2>(3), T_1841)
- node T_1843 = mux(T_1481, UInt<2>(3), T_1842)
- node T_1844 = mux(T_1479, UInt<2>(3), T_1843)
- node T_1845 = mux(T_1477, UInt<2>(3), T_1844)
- node T_1846 = mux(T_1475, UInt<2>(3), T_1845)
- node T_1847 = mux(T_1473, UInt<2>(3), T_1846)
- node T_1848 = mux(T_1471, UInt<2>(0), T_1847)
- node T_1849 = mux(T_1469, UInt<2>(1), T_1848)
- node T_1850 = mux(T_1467, UInt<2>(2), T_1849)
- node T_1851 = mux(T_1465, UInt<2>(3), T_1850)
- node T_1852 = mux(T_1463, UInt<2>(3), T_1851)
- node T_1853 = mux(T_1461, UInt<2>(3), T_1852)
- node T_1854 = mux(T_1459, UInt<2>(3), T_1853)
- node T_1855 = mux(T_1457, UInt<2>(3), T_1854)
- node T_1856 = mux(T_1455, UInt<2>(3), T_1855)
- node T_1857 = mux(T_1453, UInt<2>(3), T_1856)
- node T_1858 = mux(T_1451, UInt<2>(3), T_1857)
- node T_1859 = mux(T_1449, UInt<2>(3), T_1858)
- node T_1860 = mux(T_1447, UInt<2>(3), T_1859)
- node T_1861 = mux(T_1445, UInt<2>(3), T_1860)
- node T_1862 = mux(T_1443, UInt<2>(3), T_1861)
- node T_1863 = mux(T_1441, UInt<2>(3), T_1862)
- node T_1864 = mux(T_1439, UInt<2>(3), T_1863)
- node T_1865 = mux(T_1437, UInt<2>(3), T_1864)
- node T_1866 = mux(T_1521, UInt<3>(7), UInt<3>(7))
- node T_1867 = mux(T_1519, UInt<3>(7), T_1866)
- node T_1868 = mux(T_1517, UInt<3>(7), T_1867)
- node T_1869 = mux(T_1515, UInt<3>(7), T_1868)
- node T_1870 = mux(T_1513, UInt<3>(7), T_1869)
- node T_1871 = mux(T_1511, UInt<3>(7), T_1870)
- node T_1872 = mux(T_1509, UInt<3>(7), T_1871)
- node T_1873 = mux(T_1507, UInt<3>(7), T_1872)
- node T_1874 = mux(T_1505, UInt<3>(7), T_1873)
- node T_1875 = mux(T_1503, UInt<3>(7), T_1874)
- node T_1876 = mux(T_1501, UInt<3>(7), T_1875)
- node T_1877 = mux(T_1499, UInt<3>(7), T_1876)
- node T_1878 = mux(T_1497, UInt<3>(7), T_1877)
- node T_1879 = mux(T_1495, UInt<3>(7), T_1878)
- node T_1880 = mux(T_1493, UInt<3>(7), T_1879)
- node T_1881 = mux(T_1491, UInt<3>(7), T_1880)
- node T_1882 = mux(T_1489, UInt<3>(7), T_1881)
- node T_1883 = mux(T_1487, UInt<3>(7), T_1882)
- node T_1884 = mux(T_1485, UInt<3>(7), T_1883)
- node T_1885 = mux(T_1483, UInt<3>(7), T_1884)
- node T_1886 = mux(T_1481, UInt<3>(7), T_1885)
- node T_1887 = mux(T_1479, UInt<3>(7), T_1886)
- node T_1888 = mux(T_1477, UInt<3>(7), T_1887)
- node T_1889 = mux(T_1475, UInt<3>(7), T_1888)
- node T_1890 = mux(T_1473, UInt<3>(7), T_1889)
- node T_1891 = mux(T_1471, UInt<3>(7), T_1890)
- node T_1892 = mux(T_1469, UInt<3>(7), T_1891)
- node T_1893 = mux(T_1467, UInt<3>(7), T_1892)
- node T_1894 = mux(T_1465, UInt<3>(3), T_1893)
- node T_1895 = mux(T_1463, UInt<3>(4), T_1894)
- node T_1896 = mux(T_1461, UInt<3>(0), T_1895)
- node T_1897 = mux(T_1459, UInt<3>(1), T_1896)
- node T_1898 = mux(T_1457, UInt<3>(2), T_1897)
- node T_1899 = mux(T_1455, UInt<3>(7), T_1898)
- node T_1900 = mux(T_1453, UInt<3>(7), T_1899)
- node T_1901 = mux(T_1451, UInt<3>(7), T_1900)
- node T_1902 = mux(T_1449, UInt<3>(7), T_1901)
- node T_1903 = mux(T_1447, UInt<3>(7), T_1902)
- node T_1904 = mux(T_1445, UInt<3>(7), T_1903)
- node T_1905 = mux(T_1443, UInt<3>(7), T_1904)
- node T_1906 = mux(T_1441, UInt<3>(7), T_1905)
- node T_1907 = mux(T_1439, UInt<3>(7), T_1906)
- node T_1908 = mux(T_1437, UInt<3>(7), T_1907)
- node T_1909 = mux(T_1521, UInt<2>(3), UInt<2>(0))
- node T_1910 = mux(T_1519, UInt<2>(3), T_1909)
- node T_1911 = mux(T_1517, UInt<2>(3), T_1910)
- node T_1912 = mux(T_1515, UInt<2>(3), T_1911)
- node T_1913 = mux(T_1513, UInt<2>(3), T_1912)
- node T_1914 = mux(T_1511, UInt<2>(3), T_1913)
- node T_1915 = mux(T_1509, UInt<2>(0), T_1914)
- node T_1916 = mux(T_1507, UInt<2>(0), T_1915)
- node T_1917 = mux(T_1505, UInt<2>(0), T_1916)
- node T_1918 = mux(T_1503, UInt<2>(0), T_1917)
- node T_1919 = mux(T_1501, UInt<2>(0), T_1918)
- node T_1920 = mux(T_1499, UInt<2>(0), T_1919)
- node T_1921 = mux(T_1497, UInt<2>(0), T_1920)
- node T_1922 = mux(T_1495, UInt<2>(0), T_1921)
- node T_1923 = mux(T_1493, UInt<2>(0), T_1922)
- node T_1924 = mux(T_1491, UInt<2>(0), T_1923)
- node T_1925 = mux(T_1489, UInt<2>(0), T_1924)
- node T_1926 = mux(T_1487, UInt<2>(0), T_1925)
- node T_1927 = mux(T_1485, UInt<2>(0), T_1926)
- node T_1928 = mux(T_1483, UInt<2>(0), T_1927)
- node T_1929 = mux(T_1481, UInt<2>(0), T_1928)
- node T_1930 = mux(T_1479, UInt<2>(0), T_1929)
- node T_1931 = mux(T_1477, UInt<2>(0), T_1930)
- node T_1932 = mux(T_1475, UInt<2>(0), T_1931)
- node T_1933 = mux(T_1473, UInt<2>(0), T_1932)
- node T_1934 = mux(T_1471, UInt<2>(0), T_1933)
- node T_1935 = mux(T_1469, UInt<2>(0), T_1934)
- node T_1936 = mux(T_1467, UInt<2>(0), T_1935)
- node T_1937 = mux(T_1465, UInt<2>(1), T_1936)
- node T_1938 = mux(T_1463, UInt<2>(1), T_1937)
- node T_1939 = mux(T_1461, UInt<2>(1), T_1938)
- node T_1940 = mux(T_1459, UInt<2>(1), T_1939)
- node T_1941 = mux(T_1457, UInt<2>(1), T_1940)
- node T_1942 = mux(T_1455, UInt<2>(0), T_1941)
- node T_1943 = mux(T_1453, UInt<2>(0), T_1942)
- node T_1944 = mux(T_1451, UInt<2>(0), T_1943)
- node T_1945 = mux(T_1449, UInt<2>(0), T_1944)
- node T_1946 = mux(T_1447, UInt<2>(0), T_1945)
- node T_1947 = mux(T_1445, UInt<2>(0), T_1946)
- node T_1948 = mux(T_1443, UInt<2>(2), T_1947)
- node T_1949 = mux(T_1441, UInt<2>(2), T_1948)
- node T_1950 = mux(T_1439, UInt<2>(0), T_1949)
- node T_1951 = mux(T_1437, UInt<2>(0), T_1950)
- node T_1952 = mux(T_1521, UInt<1>(0), UInt<1>(0))
- node T_1953 = mux(T_1519, UInt<1>(0), T_1952)
- node T_1954 = mux(T_1517, UInt<1>(0), T_1953)
- node T_1955 = mux(T_1515, UInt<1>(0), T_1954)
- node T_1956 = mux(T_1513, UInt<1>(0), T_1955)
- node T_1957 = mux(T_1511, UInt<1>(0), T_1956)
- node T_1958 = mux(T_1509, UInt<1>(1), T_1957)
- node T_1959 = mux(T_1507, UInt<1>(1), T_1958)
- node T_1960 = mux(T_1505, UInt<1>(1), T_1959)
- node T_1961 = mux(T_1503, UInt<1>(1), T_1960)
- node T_1962 = mux(T_1501, UInt<1>(1), T_1961)
- node T_1963 = mux(T_1499, UInt<1>(1), T_1962)
- node T_1964 = mux(T_1497, UInt<1>(1), T_1963)
- node T_1965 = mux(T_1495, UInt<1>(1), T_1964)
- node T_1966 = mux(T_1493, UInt<1>(1), T_1965)
- node T_1967 = mux(T_1491, UInt<1>(1), T_1966)
- node T_1968 = mux(T_1489, UInt<1>(1), T_1967)
- node T_1969 = mux(T_1487, UInt<1>(1), T_1968)
- node T_1970 = mux(T_1485, UInt<1>(1), T_1969)
- node T_1971 = mux(T_1483, UInt<1>(1), T_1970)
- node T_1972 = mux(T_1481, UInt<1>(1), T_1971)
- node T_1973 = mux(T_1479, UInt<1>(1), T_1972)
- node T_1974 = mux(T_1477, UInt<1>(1), T_1973)
- node T_1975 = mux(T_1475, UInt<1>(1), T_1974)
- node T_1976 = mux(T_1473, UInt<1>(1), T_1975)
- node T_1977 = mux(T_1471, UInt<1>(0), T_1976)
- node T_1978 = mux(T_1469, UInt<1>(0), T_1977)
- node T_1979 = mux(T_1467, UInt<1>(0), T_1978)
- node T_1980 = mux(T_1465, UInt<1>(1), T_1979)
- node T_1981 = mux(T_1463, UInt<1>(1), T_1980)
- node T_1982 = mux(T_1461, UInt<1>(1), T_1981)
- node T_1983 = mux(T_1459, UInt<1>(1), T_1982)
- node T_1984 = mux(T_1457, UInt<1>(1), T_1983)
- node T_1985 = mux(T_1455, UInt<1>(0), T_1984)
- node T_1986 = mux(T_1453, UInt<1>(0), T_1985)
- node T_1987 = mux(T_1451, UInt<1>(0), T_1986)
- node T_1988 = mux(T_1449, UInt<1>(0), T_1987)
- node T_1989 = mux(T_1447, UInt<1>(0), T_1988)
- node T_1990 = mux(T_1445, UInt<1>(0), T_1989)
- node T_1991 = mux(T_1443, UInt<1>(1), T_1990)
- node T_1992 = mux(T_1441, UInt<1>(1), T_1991)
- node T_1993 = mux(T_1439, UInt<1>(1), T_1992)
- node T_1994 = mux(T_1437, UInt<1>(1), T_1993)
- node T_1995 = mux(T_1521, UInt<2>(3), UInt<2>(0))
- node T_1996 = mux(T_1519, UInt<2>(2), T_1995)
- node T_1997 = mux(T_1517, UInt<2>(1), T_1996)
- node T_1998 = mux(T_1515, UInt<2>(3), T_1997)
- node T_1999 = mux(T_1513, UInt<2>(2), T_1998)
- node T_2000 = mux(T_1511, UInt<2>(1), T_1999)
- node T_2001 = mux(T_1509, UInt<2>(0), T_2000)
- node T_2002 = mux(T_1507, UInt<2>(0), T_2001)
- node T_2003 = mux(T_1505, UInt<2>(0), T_2002)
- node T_2004 = mux(T_1503, UInt<2>(0), T_2003)
- node T_2005 = mux(T_1501, UInt<2>(0), T_2004)
- node T_2006 = mux(T_1499, UInt<2>(0), T_2005)
- node T_2007 = mux(T_1497, UInt<2>(0), T_2006)
- node T_2008 = mux(T_1495, UInt<2>(0), T_2007)
- node T_2009 = mux(T_1493, UInt<2>(0), T_2008)
- node T_2010 = mux(T_1491, UInt<2>(0), T_2009)
- node T_2011 = mux(T_1489, UInt<2>(0), T_2010)
- node T_2012 = mux(T_1487, UInt<2>(0), T_2011)
- node T_2013 = mux(T_1485, UInt<2>(0), T_2012)
- node T_2014 = mux(T_1483, UInt<2>(0), T_2013)
- node T_2015 = mux(T_1481, UInt<2>(0), T_2014)
- node T_2016 = mux(T_1479, UInt<2>(0), T_2015)
- node T_2017 = mux(T_1477, UInt<2>(0), T_2016)
- node T_2018 = mux(T_1475, UInt<2>(0), T_2017)
- node T_2019 = mux(T_1473, UInt<2>(0), T_2018)
- node T_2020 = mux(T_1471, UInt<2>(0), T_2019)
- node T_2021 = mux(T_1469, UInt<2>(0), T_2020)
- node T_2022 = mux(T_1467, UInt<2>(0), T_2021)
- node T_2023 = mux(T_1465, UInt<2>(0), T_2022)
- node T_2024 = mux(T_1463, UInt<2>(0), T_2023)
- node T_2025 = mux(T_1461, UInt<2>(0), T_2024)
- node T_2026 = mux(T_1459, UInt<2>(0), T_2025)
- node T_2027 = mux(T_1457, UInt<2>(0), T_2026)
- node T_2028 = mux(T_1455, UInt<2>(0), T_2027)
- node T_2029 = mux(T_1453, UInt<2>(0), T_2028)
- node T_2030 = mux(T_1451, UInt<2>(0), T_2029)
- node T_2031 = mux(T_1449, UInt<2>(0), T_2030)
- node T_2032 = mux(T_1447, UInt<2>(0), T_2031)
- node T_2033 = mux(T_1445, UInt<2>(0), T_2032)
- node T_2034 = mux(T_1443, UInt<2>(0), T_2033)
- node T_2035 = mux(T_1441, UInt<2>(0), T_2034)
- node T_2036 = mux(T_1439, UInt<2>(0), T_2035)
- node T_2037 = mux(T_1437, UInt<2>(0), T_2036)
+ node T_831 = and(UInt<7>(127), ctrl.inst)
+ node T_832 = eq(T_831, UInt<6>(55))
+ node T_833 = and(UInt<7>(127), ctrl.inst)
+ node T_834 = eq(T_833, UInt<5>(23))
+ node T_835 = and(UInt<7>(127), ctrl.inst)
+ node T_836 = eq(T_835, UInt<7>(111))
+ node T_837 = and(UInt<15>(28799), ctrl.inst)
+ node T_838 = eq(T_837, UInt<7>(103))
+ node T_839 = and(UInt<15>(28799), ctrl.inst)
+ node T_840 = eq(T_839, UInt<7>(99))
+ node T_841 = and(UInt<15>(28799), ctrl.inst)
+ node T_842 = eq(T_841, UInt<13>(4195))
+ node T_843 = and(UInt<15>(28799), ctrl.inst)
+ node T_844 = eq(T_843, UInt<15>(16483))
+ node T_845 = and(UInt<15>(28799), ctrl.inst)
+ node T_846 = eq(T_845, UInt<15>(20579))
+ node T_847 = and(UInt<15>(28799), ctrl.inst)
+ node T_848 = eq(T_847, UInt<15>(24675))
+ node T_849 = and(UInt<15>(28799), ctrl.inst)
+ node T_850 = eq(T_849, UInt<15>(28771))
+ node T_851 = and(UInt<15>(28799), ctrl.inst)
+ node T_852 = eq(T_851, UInt<2>(3))
+ node T_853 = and(UInt<15>(28799), ctrl.inst)
+ node T_854 = eq(T_853, UInt<13>(4099))
+ node T_855 = and(UInt<15>(28799), ctrl.inst)
+ node T_856 = eq(T_855, UInt<14>(8195))
+ node T_857 = and(UInt<15>(28799), ctrl.inst)
+ node T_858 = eq(T_857, UInt<15>(16387))
+ node T_859 = and(UInt<15>(28799), ctrl.inst)
+ node T_860 = eq(T_859, UInt<15>(20483))
+ node T_861 = and(UInt<15>(28799), ctrl.inst)
+ node T_862 = eq(T_861, UInt<6>(35))
+ node T_863 = and(UInt<15>(28799), ctrl.inst)
+ node T_864 = eq(T_863, UInt<13>(4131))
+ node T_865 = and(UInt<15>(28799), ctrl.inst)
+ node T_866 = eq(T_865, UInt<14>(8227))
+ node T_867 = and(UInt<15>(28799), ctrl.inst)
+ node T_868 = eq(T_867, UInt<5>(19))
+ node T_869 = and(UInt<15>(28799), ctrl.inst)
+ node T_870 = eq(T_869, UInt<14>(8211))
+ node T_871 = and(UInt<15>(28799), ctrl.inst)
+ node T_872 = eq(T_871, UInt<14>(12307))
+ node T_873 = and(UInt<15>(28799), ctrl.inst)
+ node T_874 = eq(T_873, UInt<15>(16403))
+ node T_875 = and(UInt<15>(28799), ctrl.inst)
+ node T_876 = eq(T_875, UInt<15>(24595))
+ node T_877 = and(UInt<15>(28799), ctrl.inst)
+ node T_878 = eq(T_877, UInt<15>(28691))
+ node T_879 = and(UInt<32>(4261441663), ctrl.inst)
+ node T_880 = eq(T_879, UInt<13>(4115))
+ node T_881 = and(UInt<32>(4261441663), ctrl.inst)
+ node T_882 = eq(T_881, UInt<15>(20499))
+ node T_883 = and(UInt<32>(4261441663), ctrl.inst)
+ node T_884 = eq(T_883, UInt<31>(1073762323))
+ node T_885 = and(UInt<32>(4261441663), ctrl.inst)
+ node T_886 = eq(T_885, UInt<6>(51))
+ node T_887 = and(UInt<32>(4261441663), ctrl.inst)
+ node T_888 = eq(T_887, UInt<31>(1073741875))
+ node T_889 = and(UInt<32>(4261441663), ctrl.inst)
+ node T_890 = eq(T_889, UInt<13>(4147))
+ node T_891 = and(UInt<32>(4261441663), ctrl.inst)
+ node T_892 = eq(T_891, UInt<14>(8243))
+ node T_893 = and(UInt<32>(4261441663), ctrl.inst)
+ node T_894 = eq(T_893, UInt<14>(12339))
+ node T_895 = and(UInt<32>(4261441663), ctrl.inst)
+ node T_896 = eq(T_895, UInt<15>(16435))
+ node T_897 = and(UInt<32>(4261441663), ctrl.inst)
+ node T_898 = eq(T_897, UInt<15>(20531))
+ node T_899 = and(UInt<32>(4261441663), ctrl.inst)
+ node T_900 = eq(T_899, UInt<31>(1073762355))
+ node T_901 = and(UInt<32>(4261441663), ctrl.inst)
+ node T_902 = eq(T_901, UInt<15>(24627))
+ node T_903 = and(UInt<32>(4261441663), ctrl.inst)
+ node T_904 = eq(T_903, UInt<15>(28723))
+ node T_905 = and(UInt<15>(28799), ctrl.inst)
+ node T_906 = eq(T_905, UInt<13>(4211))
+ node T_907 = and(UInt<15>(28799), ctrl.inst)
+ node T_908 = eq(T_907, UInt<14>(8307))
+ node T_909 = and(UInt<15>(28799), ctrl.inst)
+ node T_910 = eq(T_909, UInt<14>(12403))
+ node T_911 = and(UInt<15>(28799), ctrl.inst)
+ node T_912 = eq(T_911, UInt<15>(20595))
+ node T_913 = and(UInt<15>(28799), ctrl.inst)
+ node T_914 = eq(T_913, UInt<15>(24691))
+ node T_915 = and(UInt<15>(28799), ctrl.inst)
+ node T_916 = eq(T_915, UInt<15>(28787))
+ node T_917 = mux(T_916, UInt<1>(0), UInt<1>(0))
+ node T_918 = mux(T_914, UInt<1>(0), T_917)
+ node T_919 = mux(T_912, UInt<1>(0), T_918)
+ node T_920 = mux(T_910, UInt<1>(0), T_919)
+ node T_921 = mux(T_908, UInt<1>(0), T_920)
+ node T_922 = mux(T_906, UInt<1>(0), T_921)
+ node T_923 = mux(T_904, UInt<1>(0), T_922)
+ node T_924 = mux(T_902, UInt<1>(0), T_923)
+ node T_925 = mux(T_900, UInt<1>(0), T_924)
+ node T_926 = mux(T_898, UInt<1>(0), T_925)
+ node T_927 = mux(T_896, UInt<1>(0), T_926)
+ node T_928 = mux(T_894, UInt<1>(0), T_927)
+ node T_929 = mux(T_892, UInt<1>(0), T_928)
+ node T_930 = mux(T_890, UInt<1>(0), T_929)
+ node T_931 = mux(T_888, UInt<1>(0), T_930)
+ node T_932 = mux(T_886, UInt<1>(0), T_931)
+ node T_933 = mux(T_884, UInt<1>(0), T_932)
+ node T_934 = mux(T_882, UInt<1>(0), T_933)
+ node T_935 = mux(T_880, UInt<1>(0), T_934)
+ node T_936 = mux(T_878, UInt<1>(0), T_935)
+ node T_937 = mux(T_876, UInt<1>(0), T_936)
+ node T_938 = mux(T_874, UInt<1>(0), T_937)
+ node T_939 = mux(T_872, UInt<1>(0), T_938)
+ node T_940 = mux(T_870, UInt<1>(0), T_939)
+ node T_941 = mux(T_868, UInt<1>(0), T_940)
+ node T_942 = mux(T_866, UInt<1>(0), T_941)
+ node T_943 = mux(T_864, UInt<1>(0), T_942)
+ node T_944 = mux(T_862, UInt<1>(0), T_943)
+ node T_945 = mux(T_860, UInt<1>(0), T_944)
+ node T_946 = mux(T_858, UInt<1>(0), T_945)
+ node T_947 = mux(T_856, UInt<1>(0), T_946)
+ node T_948 = mux(T_854, UInt<1>(0), T_947)
+ node T_949 = mux(T_852, UInt<1>(0), T_948)
+ node T_950 = mux(T_850, UInt<1>(0), T_949)
+ node T_951 = mux(T_848, UInt<1>(0), T_950)
+ node T_952 = mux(T_846, UInt<1>(0), T_951)
+ node T_953 = mux(T_844, UInt<1>(0), T_952)
+ node T_954 = mux(T_842, UInt<1>(0), T_953)
+ node T_955 = mux(T_840, UInt<1>(0), T_954)
+ node T_956 = mux(T_838, UInt<1>(1), T_955)
+ node T_957 = mux(T_836, UInt<1>(1), T_956)
+ node T_958 = mux(T_834, UInt<1>(0), T_957)
+ node T_959 = mux(T_832, UInt<1>(0), T_958)
+ node T_960 = mux(T_916, UInt<1>(1), UInt<1>(1))
+ node T_961 = mux(T_914, UInt<1>(1), T_960)
+ node T_962 = mux(T_912, UInt<1>(1), T_961)
+ node T_963 = mux(T_910, UInt<1>(0), T_962)
+ node T_964 = mux(T_908, UInt<1>(0), T_963)
+ node T_965 = mux(T_906, UInt<1>(0), T_964)
+ node T_966 = mux(T_904, UInt<1>(0), T_965)
+ node T_967 = mux(T_902, UInt<1>(0), T_966)
+ node T_968 = mux(T_900, UInt<1>(0), T_967)
+ node T_969 = mux(T_898, UInt<1>(0), T_968)
+ node T_970 = mux(T_896, UInt<1>(0), T_969)
+ node T_971 = mux(T_894, UInt<1>(0), T_970)
+ node T_972 = mux(T_892, UInt<1>(0), T_971)
+ node T_973 = mux(T_890, UInt<1>(0), T_972)
+ node T_974 = mux(T_888, UInt<1>(0), T_973)
+ node T_975 = mux(T_886, UInt<1>(0), T_974)
+ node T_976 = mux(T_884, UInt<1>(0), T_975)
+ node T_977 = mux(T_882, UInt<1>(0), T_976)
+ node T_978 = mux(T_880, UInt<1>(0), T_977)
+ node T_979 = mux(T_878, UInt<1>(0), T_978)
+ node T_980 = mux(T_876, UInt<1>(0), T_979)
+ node T_981 = mux(T_874, UInt<1>(0), T_980)
+ node T_982 = mux(T_872, UInt<1>(0), T_981)
+ node T_983 = mux(T_870, UInt<1>(0), T_982)
+ node T_984 = mux(T_868, UInt<1>(0), T_983)
+ node T_985 = mux(T_866, UInt<1>(0), T_984)
+ node T_986 = mux(T_864, UInt<1>(0), T_985)
+ node T_987 = mux(T_862, UInt<1>(0), T_986)
+ node T_988 = mux(T_860, UInt<1>(0), T_987)
+ node T_989 = mux(T_858, UInt<1>(0), T_988)
+ node T_990 = mux(T_856, UInt<1>(0), T_989)
+ node T_991 = mux(T_854, UInt<1>(0), T_990)
+ node T_992 = mux(T_852, UInt<1>(0), T_991)
+ node T_993 = mux(T_850, UInt<1>(1), T_992)
+ node T_994 = mux(T_848, UInt<1>(1), T_993)
+ node T_995 = mux(T_846, UInt<1>(1), T_994)
+ node T_996 = mux(T_844, UInt<1>(1), T_995)
+ node T_997 = mux(T_842, UInt<1>(1), T_996)
+ node T_998 = mux(T_840, UInt<1>(1), T_997)
+ node T_999 = mux(T_838, UInt<1>(0), T_998)
+ node T_1000 = mux(T_836, UInt<1>(1), T_999)
+ node T_1001 = mux(T_834, UInt<1>(1), T_1000)
+ node T_1002 = mux(T_832, UInt<1>(1), T_1001)
+ node T_1003 = mux(T_916, UInt<1>(1), UInt<1>(0))
+ node T_1004 = mux(T_914, UInt<1>(1), T_1003)
+ node T_1005 = mux(T_912, UInt<1>(1), T_1004)
+ node T_1006 = mux(T_910, UInt<1>(0), T_1005)
+ node T_1007 = mux(T_908, UInt<1>(0), T_1006)
+ node T_1008 = mux(T_906, UInt<1>(0), T_1007)
+ node T_1009 = mux(T_904, UInt<1>(0), T_1008)
+ node T_1010 = mux(T_902, UInt<1>(0), T_1009)
+ node T_1011 = mux(T_900, UInt<1>(0), T_1010)
+ node T_1012 = mux(T_898, UInt<1>(0), T_1011)
+ node T_1013 = mux(T_896, UInt<1>(0), T_1012)
+ node T_1014 = mux(T_894, UInt<1>(0), T_1013)
+ node T_1015 = mux(T_892, UInt<1>(0), T_1014)
+ node T_1016 = mux(T_890, UInt<1>(0), T_1015)
+ node T_1017 = mux(T_888, UInt<1>(0), T_1016)
+ node T_1018 = mux(T_886, UInt<1>(0), T_1017)
+ node T_1019 = mux(T_884, UInt<1>(1), T_1018)
+ node T_1020 = mux(T_882, UInt<1>(1), T_1019)
+ node T_1021 = mux(T_880, UInt<1>(1), T_1020)
+ node T_1022 = mux(T_878, UInt<1>(1), T_1021)
+ node T_1023 = mux(T_876, UInt<1>(1), T_1022)
+ node T_1024 = mux(T_874, UInt<1>(1), T_1023)
+ node T_1025 = mux(T_872, UInt<1>(1), T_1024)
+ node T_1026 = mux(T_870, UInt<1>(1), T_1025)
+ node T_1027 = mux(T_868, UInt<1>(1), T_1026)
+ node T_1028 = mux(T_866, UInt<1>(1), T_1027)
+ node T_1029 = mux(T_864, UInt<1>(1), T_1028)
+ node T_1030 = mux(T_862, UInt<1>(1), T_1029)
+ node T_1031 = mux(T_860, UInt<1>(1), T_1030)
+ node T_1032 = mux(T_858, UInt<1>(1), T_1031)
+ node T_1033 = mux(T_856, UInt<1>(1), T_1032)
+ node T_1034 = mux(T_854, UInt<1>(1), T_1033)
+ node T_1035 = mux(T_852, UInt<1>(1), T_1034)
+ node T_1036 = mux(T_850, UInt<1>(1), T_1035)
+ node T_1037 = mux(T_848, UInt<1>(1), T_1036)
+ node T_1038 = mux(T_846, UInt<1>(1), T_1037)
+ node T_1039 = mux(T_844, UInt<1>(1), T_1038)
+ node T_1040 = mux(T_842, UInt<1>(1), T_1039)
+ node T_1041 = mux(T_840, UInt<1>(1), T_1040)
+ node T_1042 = mux(T_838, UInt<1>(1), T_1041)
+ node T_1043 = mux(T_836, UInt<1>(1), T_1042)
+ node T_1044 = mux(T_834, UInt<1>(1), T_1043)
+ node T_1045 = mux(T_832, UInt<1>(1), T_1044)
+ node T_1046 = mux(T_916, UInt<3>(5), UInt<3>(7))
+ node T_1047 = mux(T_914, UInt<3>(5), T_1046)
+ node T_1048 = mux(T_912, UInt<3>(5), T_1047)
+ node T_1049 = mux(T_910, UInt<3>(5), T_1048)
+ node T_1050 = mux(T_908, UInt<3>(5), T_1049)
+ node T_1051 = mux(T_906, UInt<3>(5), T_1050)
+ node T_1052 = mux(T_904, UInt<3>(7), T_1051)
+ node T_1053 = mux(T_902, UInt<3>(7), T_1052)
+ node T_1054 = mux(T_900, UInt<3>(7), T_1053)
+ node T_1055 = mux(T_898, UInt<3>(7), T_1054)
+ node T_1056 = mux(T_896, UInt<3>(7), T_1055)
+ node T_1057 = mux(T_894, UInt<3>(7), T_1056)
+ node T_1058 = mux(T_892, UInt<3>(7), T_1057)
+ node T_1059 = mux(T_890, UInt<3>(7), T_1058)
+ node T_1060 = mux(T_888, UInt<3>(7), T_1059)
+ node T_1061 = mux(T_886, UInt<3>(7), T_1060)
+ node T_1062 = mux(T_884, UInt<3>(0), T_1061)
+ node T_1063 = mux(T_882, UInt<3>(0), T_1062)
+ node T_1064 = mux(T_880, UInt<3>(0), T_1063)
+ node T_1065 = mux(T_878, UInt<3>(0), T_1064)
+ node T_1066 = mux(T_876, UInt<3>(0), T_1065)
+ node T_1067 = mux(T_874, UInt<3>(0), T_1066)
+ node T_1068 = mux(T_872, UInt<3>(0), T_1067)
+ node T_1069 = mux(T_870, UInt<3>(0), T_1068)
+ node T_1070 = mux(T_868, UInt<3>(0), T_1069)
+ node T_1071 = mux(T_866, UInt<3>(1), T_1070)
+ node T_1072 = mux(T_864, UInt<3>(1), T_1071)
+ node T_1073 = mux(T_862, UInt<3>(1), T_1072)
+ node T_1074 = mux(T_860, UInt<3>(0), T_1073)
+ node T_1075 = mux(T_858, UInt<3>(0), T_1074)
+ node T_1076 = mux(T_856, UInt<3>(0), T_1075)
+ node T_1077 = mux(T_854, UInt<3>(0), T_1076)
+ node T_1078 = mux(T_852, UInt<3>(0), T_1077)
+ node T_1079 = mux(T_850, UInt<3>(4), T_1078)
+ node T_1080 = mux(T_848, UInt<3>(4), T_1079)
+ node T_1081 = mux(T_846, UInt<3>(4), T_1080)
+ node T_1082 = mux(T_844, UInt<3>(4), T_1081)
+ node T_1083 = mux(T_842, UInt<3>(4), T_1082)
+ node T_1084 = mux(T_840, UInt<3>(4), T_1083)
+ node T_1085 = mux(T_838, UInt<3>(0), T_1084)
+ node T_1086 = mux(T_836, UInt<3>(3), T_1085)
+ node T_1087 = mux(T_834, UInt<3>(2), T_1086)
+ node T_1088 = mux(T_832, UInt<3>(2), T_1087)
+ node T_1089 = mux(T_916, UInt<4>(11), UInt<4>(15))
+ node T_1090 = mux(T_914, UInt<4>(11), T_1089)
+ node T_1091 = mux(T_912, UInt<4>(11), T_1090)
+ node T_1092 = mux(T_910, UInt<4>(10), T_1091)
+ node T_1093 = mux(T_908, UInt<4>(10), T_1092)
+ node T_1094 = mux(T_906, UInt<4>(10), T_1093)
+ node T_1095 = mux(T_904, UInt<4>(2), T_1094)
+ node T_1096 = mux(T_902, UInt<4>(3), T_1095)
+ node T_1097 = mux(T_900, UInt<4>(9), T_1096)
+ node T_1098 = mux(T_898, UInt<4>(8), T_1097)
+ node T_1099 = mux(T_896, UInt<4>(4), T_1098)
+ node T_1100 = mux(T_894, UInt<4>(7), T_1099)
+ node T_1101 = mux(T_892, UInt<4>(5), T_1100)
+ node T_1102 = mux(T_890, UInt<4>(6), T_1101)
+ node T_1103 = mux(T_888, UInt<4>(1), T_1102)
+ node T_1104 = mux(T_886, UInt<4>(0), T_1103)
+ node T_1105 = mux(T_884, UInt<4>(9), T_1104)
+ node T_1106 = mux(T_882, UInt<4>(8), T_1105)
+ node T_1107 = mux(T_880, UInt<4>(6), T_1106)
+ node T_1108 = mux(T_878, UInt<4>(2), T_1107)
+ node T_1109 = mux(T_876, UInt<4>(3), T_1108)
+ node T_1110 = mux(T_874, UInt<4>(4), T_1109)
+ node T_1111 = mux(T_872, UInt<4>(7), T_1110)
+ node T_1112 = mux(T_870, UInt<4>(5), T_1111)
+ node T_1113 = mux(T_868, UInt<4>(0), T_1112)
+ node T_1114 = mux(T_866, UInt<4>(0), T_1113)
+ node T_1115 = mux(T_864, UInt<4>(0), T_1114)
+ node T_1116 = mux(T_862, UInt<4>(0), T_1115)
+ node T_1117 = mux(T_860, UInt<4>(0), T_1116)
+ node T_1118 = mux(T_858, UInt<4>(0), T_1117)
+ node T_1119 = mux(T_856, UInt<4>(0), T_1118)
+ node T_1120 = mux(T_854, UInt<4>(0), T_1119)
+ node T_1121 = mux(T_852, UInt<4>(0), T_1120)
+ node T_1122 = mux(T_850, UInt<4>(0), T_1121)
+ node T_1123 = mux(T_848, UInt<4>(0), T_1122)
+ node T_1124 = mux(T_846, UInt<4>(0), T_1123)
+ node T_1125 = mux(T_844, UInt<4>(0), T_1124)
+ node T_1126 = mux(T_842, UInt<4>(0), T_1125)
+ node T_1127 = mux(T_840, UInt<4>(0), T_1126)
+ node T_1128 = mux(T_838, UInt<4>(0), T_1127)
+ node T_1129 = mux(T_836, UInt<4>(0), T_1128)
+ node T_1130 = mux(T_834, UInt<4>(0), T_1129)
+ node T_1131 = mux(T_832, UInt<4>(11), T_1130)
+ node T_1132 = mux(T_916, UInt<3>(7), UInt<3>(7))
+ node T_1133 = mux(T_914, UInt<3>(7), T_1132)
+ node T_1134 = mux(T_912, UInt<3>(7), T_1133)
+ node T_1135 = mux(T_910, UInt<3>(7), T_1134)
+ node T_1136 = mux(T_908, UInt<3>(7), T_1135)
+ node T_1137 = mux(T_906, UInt<3>(7), T_1136)
+ node T_1138 = mux(T_904, UInt<3>(7), T_1137)
+ node T_1139 = mux(T_902, UInt<3>(7), T_1138)
+ node T_1140 = mux(T_900, UInt<3>(7), T_1139)
+ node T_1141 = mux(T_898, UInt<3>(7), T_1140)
+ node T_1142 = mux(T_896, UInt<3>(7), T_1141)
+ node T_1143 = mux(T_894, UInt<3>(7), T_1142)
+ node T_1144 = mux(T_892, UInt<3>(7), T_1143)
+ node T_1145 = mux(T_890, UInt<3>(7), T_1144)
+ node T_1146 = mux(T_888, UInt<3>(7), T_1145)
+ node T_1147 = mux(T_886, UInt<3>(7), T_1146)
+ node T_1148 = mux(T_884, UInt<3>(7), T_1147)
+ node T_1149 = mux(T_882, UInt<3>(7), T_1148)
+ node T_1150 = mux(T_880, UInt<3>(7), T_1149)
+ node T_1151 = mux(T_878, UInt<3>(7), T_1150)
+ node T_1152 = mux(T_876, UInt<3>(7), T_1151)
+ node T_1153 = mux(T_874, UInt<3>(7), T_1152)
+ node T_1154 = mux(T_872, UInt<3>(7), T_1153)
+ node T_1155 = mux(T_870, UInt<3>(7), T_1154)
+ node T_1156 = mux(T_868, UInt<3>(7), T_1155)
+ node T_1157 = mux(T_866, UInt<3>(7), T_1156)
+ node T_1158 = mux(T_864, UInt<3>(7), T_1157)
+ node T_1159 = mux(T_862, UInt<3>(7), T_1158)
+ node T_1160 = mux(T_860, UInt<3>(7), T_1159)
+ node T_1161 = mux(T_858, UInt<3>(7), T_1160)
+ node T_1162 = mux(T_856, UInt<3>(7), T_1161)
+ node T_1163 = mux(T_854, UInt<3>(7), T_1162)
+ node T_1164 = mux(T_852, UInt<3>(7), T_1163)
+ node T_1165 = mux(T_850, UInt<3>(4), T_1164)
+ node T_1166 = mux(T_848, UInt<3>(0), T_1165)
+ node T_1167 = mux(T_846, UInt<3>(5), T_1166)
+ node T_1168 = mux(T_844, UInt<3>(1), T_1167)
+ node T_1169 = mux(T_842, UInt<3>(6), T_1168)
+ node T_1170 = mux(T_840, UInt<3>(2), T_1169)
+ node T_1171 = mux(T_838, UInt<3>(7), T_1170)
+ node T_1172 = mux(T_836, UInt<3>(7), T_1171)
+ node T_1173 = mux(T_834, UInt<3>(7), T_1172)
+ node T_1174 = mux(T_832, UInt<3>(7), T_1173)
+ node T_1175 = mux(T_916, UInt<1>(0), UInt<1>(0))
+ node T_1176 = mux(T_914, UInt<1>(0), T_1175)
+ node T_1177 = mux(T_912, UInt<1>(0), T_1176)
+ node T_1178 = mux(T_910, UInt<1>(0), T_1177)
+ node T_1179 = mux(T_908, UInt<1>(0), T_1178)
+ node T_1180 = mux(T_906, UInt<1>(0), T_1179)
+ node T_1181 = mux(T_904, UInt<1>(0), T_1180)
+ node T_1182 = mux(T_902, UInt<1>(0), T_1181)
+ node T_1183 = mux(T_900, UInt<1>(0), T_1182)
+ node T_1184 = mux(T_898, UInt<1>(0), T_1183)
+ node T_1185 = mux(T_896, UInt<1>(0), T_1184)
+ node T_1186 = mux(T_894, UInt<1>(0), T_1185)
+ node T_1187 = mux(T_892, UInt<1>(0), T_1186)
+ node T_1188 = mux(T_890, UInt<1>(0), T_1187)
+ node T_1189 = mux(T_888, UInt<1>(0), T_1188)
+ node T_1190 = mux(T_886, UInt<1>(0), T_1189)
+ node T_1191 = mux(T_884, UInt<1>(0), T_1190)
+ node T_1192 = mux(T_882, UInt<1>(0), T_1191)
+ node T_1193 = mux(T_880, UInt<1>(0), T_1192)
+ node T_1194 = mux(T_878, UInt<1>(0), T_1193)
+ node T_1195 = mux(T_876, UInt<1>(0), T_1194)
+ node T_1196 = mux(T_874, UInt<1>(0), T_1195)
+ node T_1197 = mux(T_872, UInt<1>(0), T_1196)
+ node T_1198 = mux(T_870, UInt<1>(0), T_1197)
+ node T_1199 = mux(T_868, UInt<1>(0), T_1198)
+ node T_1200 = mux(T_866, UInt<1>(0), T_1199)
+ node T_1201 = mux(T_864, UInt<1>(0), T_1200)
+ node T_1202 = mux(T_862, UInt<1>(0), T_1201)
+ node T_1203 = mux(T_860, UInt<1>(0), T_1202)
+ node T_1204 = mux(T_858, UInt<1>(0), T_1203)
+ node T_1205 = mux(T_856, UInt<1>(0), T_1204)
+ node T_1206 = mux(T_854, UInt<1>(0), T_1205)
+ node T_1207 = mux(T_852, UInt<1>(0), T_1206)
+ node T_1208 = mux(T_850, UInt<1>(0), T_1207)
+ node T_1209 = mux(T_848, UInt<1>(0), T_1208)
+ node T_1210 = mux(T_846, UInt<1>(0), T_1209)
+ node T_1211 = mux(T_844, UInt<1>(0), T_1210)
+ node T_1212 = mux(T_842, UInt<1>(0), T_1211)
+ node T_1213 = mux(T_840, UInt<1>(0), T_1212)
+ node T_1214 = mux(T_838, UInt<1>(1), T_1213)
+ node T_1215 = mux(T_836, UInt<1>(1), T_1214)
+ node T_1216 = mux(T_834, UInt<1>(0), T_1215)
+ node T_1217 = mux(T_832, UInt<1>(0), T_1216)
+ node T_1218 = mux(T_916, UInt<2>(3), UInt<2>(3))
+ node T_1219 = mux(T_914, UInt<2>(3), T_1218)
+ node T_1220 = mux(T_912, UInt<2>(3), T_1219)
+ node T_1221 = mux(T_910, UInt<2>(3), T_1220)
+ node T_1222 = mux(T_908, UInt<2>(3), T_1221)
+ node T_1223 = mux(T_906, UInt<2>(3), T_1222)
+ node T_1224 = mux(T_904, UInt<2>(3), T_1223)
+ node T_1225 = mux(T_902, UInt<2>(3), T_1224)
+ node T_1226 = mux(T_900, UInt<2>(3), T_1225)
+ node T_1227 = mux(T_898, UInt<2>(3), T_1226)
+ node T_1228 = mux(T_896, UInt<2>(3), T_1227)
+ node T_1229 = mux(T_894, UInt<2>(3), T_1228)
+ node T_1230 = mux(T_892, UInt<2>(3), T_1229)
+ node T_1231 = mux(T_890, UInt<2>(3), T_1230)
+ node T_1232 = mux(T_888, UInt<2>(3), T_1231)
+ node T_1233 = mux(T_886, UInt<2>(3), T_1232)
+ node T_1234 = mux(T_884, UInt<2>(3), T_1233)
+ node T_1235 = mux(T_882, UInt<2>(3), T_1234)
+ node T_1236 = mux(T_880, UInt<2>(3), T_1235)
+ node T_1237 = mux(T_878, UInt<2>(3), T_1236)
+ node T_1238 = mux(T_876, UInt<2>(3), T_1237)
+ node T_1239 = mux(T_874, UInt<2>(3), T_1238)
+ node T_1240 = mux(T_872, UInt<2>(3), T_1239)
+ node T_1241 = mux(T_870, UInt<2>(3), T_1240)
+ node T_1242 = mux(T_868, UInt<2>(3), T_1241)
+ node T_1243 = mux(T_866, UInt<2>(0), T_1242)
+ node T_1244 = mux(T_864, UInt<2>(1), T_1243)
+ node T_1245 = mux(T_862, UInt<2>(2), T_1244)
+ node T_1246 = mux(T_860, UInt<2>(3), T_1245)
+ node T_1247 = mux(T_858, UInt<2>(3), T_1246)
+ node T_1248 = mux(T_856, UInt<2>(3), T_1247)
+ node T_1249 = mux(T_854, UInt<2>(3), T_1248)
+ node T_1250 = mux(T_852, UInt<2>(3), T_1249)
+ node T_1251 = mux(T_850, UInt<2>(3), T_1250)
+ node T_1252 = mux(T_848, UInt<2>(3), T_1251)
+ node T_1253 = mux(T_846, UInt<2>(3), T_1252)
+ node T_1254 = mux(T_844, UInt<2>(3), T_1253)
+ node T_1255 = mux(T_842, UInt<2>(3), T_1254)
+ node T_1256 = mux(T_840, UInt<2>(3), T_1255)
+ node T_1257 = mux(T_838, UInt<2>(3), T_1256)
+ node T_1258 = mux(T_836, UInt<2>(3), T_1257)
+ node T_1259 = mux(T_834, UInt<2>(3), T_1258)
+ node T_1260 = mux(T_832, UInt<2>(3), T_1259)
+ node T_1261 = mux(T_916, UInt<3>(7), UInt<3>(7))
+ node T_1262 = mux(T_914, UInt<3>(7), T_1261)
+ node T_1263 = mux(T_912, UInt<3>(7), T_1262)
+ node T_1264 = mux(T_910, UInt<3>(7), T_1263)
+ node T_1265 = mux(T_908, UInt<3>(7), T_1264)
+ node T_1266 = mux(T_906, UInt<3>(7), T_1265)
+ node T_1267 = mux(T_904, UInt<3>(7), T_1266)
+ node T_1268 = mux(T_902, UInt<3>(7), T_1267)
+ node T_1269 = mux(T_900, UInt<3>(7), T_1268)
+ node T_1270 = mux(T_898, UInt<3>(7), T_1269)
+ node T_1271 = mux(T_896, UInt<3>(7), T_1270)
+ node T_1272 = mux(T_894, UInt<3>(7), T_1271)
+ node T_1273 = mux(T_892, UInt<3>(7), T_1272)
+ node T_1274 = mux(T_890, UInt<3>(7), T_1273)
+ node T_1275 = mux(T_888, UInt<3>(7), T_1274)
+ node T_1276 = mux(T_886, UInt<3>(7), T_1275)
+ node T_1277 = mux(T_884, UInt<3>(7), T_1276)
+ node T_1278 = mux(T_882, UInt<3>(7), T_1277)
+ node T_1279 = mux(T_880, UInt<3>(7), T_1278)
+ node T_1280 = mux(T_878, UInt<3>(7), T_1279)
+ node T_1281 = mux(T_876, UInt<3>(7), T_1280)
+ node T_1282 = mux(T_874, UInt<3>(7), T_1281)
+ node T_1283 = mux(T_872, UInt<3>(7), T_1282)
+ node T_1284 = mux(T_870, UInt<3>(7), T_1283)
+ node T_1285 = mux(T_868, UInt<3>(7), T_1284)
+ node T_1286 = mux(T_866, UInt<3>(7), T_1285)
+ node T_1287 = mux(T_864, UInt<3>(7), T_1286)
+ node T_1288 = mux(T_862, UInt<3>(7), T_1287)
+ node T_1289 = mux(T_860, UInt<3>(3), T_1288)
+ node T_1290 = mux(T_858, UInt<3>(4), T_1289)
+ node T_1291 = mux(T_856, UInt<3>(0), T_1290)
+ node T_1292 = mux(T_854, UInt<3>(1), T_1291)
+ node T_1293 = mux(T_852, UInt<3>(2), T_1292)
+ node T_1294 = mux(T_850, UInt<3>(7), T_1293)
+ node T_1295 = mux(T_848, UInt<3>(7), T_1294)
+ node T_1296 = mux(T_846, UInt<3>(7), T_1295)
+ node T_1297 = mux(T_844, UInt<3>(7), T_1296)
+ node T_1298 = mux(T_842, UInt<3>(7), T_1297)
+ node T_1299 = mux(T_840, UInt<3>(7), T_1298)
+ node T_1300 = mux(T_838, UInt<3>(7), T_1299)
+ node T_1301 = mux(T_836, UInt<3>(7), T_1300)
+ node T_1302 = mux(T_834, UInt<3>(7), T_1301)
+ node T_1303 = mux(T_832, UInt<3>(7), T_1302)
+ node T_1304 = mux(T_916, UInt<2>(3), UInt<2>(0))
+ node T_1305 = mux(T_914, UInt<2>(3), T_1304)
+ node T_1306 = mux(T_912, UInt<2>(3), T_1305)
+ node T_1307 = mux(T_910, UInt<2>(3), T_1306)
+ node T_1308 = mux(T_908, UInt<2>(3), T_1307)
+ node T_1309 = mux(T_906, UInt<2>(3), T_1308)
+ node T_1310 = mux(T_904, UInt<2>(0), T_1309)
+ node T_1311 = mux(T_902, UInt<2>(0), T_1310)
+ node T_1312 = mux(T_900, UInt<2>(0), T_1311)
+ node T_1313 = mux(T_898, UInt<2>(0), T_1312)
+ node T_1314 = mux(T_896, UInt<2>(0), T_1313)
+ node T_1315 = mux(T_894, UInt<2>(0), T_1314)
+ node T_1316 = mux(T_892, UInt<2>(0), T_1315)
+ node T_1317 = mux(T_890, UInt<2>(0), T_1316)
+ node T_1318 = mux(T_888, UInt<2>(0), T_1317)
+ node T_1319 = mux(T_886, UInt<2>(0), T_1318)
+ node T_1320 = mux(T_884, UInt<2>(0), T_1319)
+ node T_1321 = mux(T_882, UInt<2>(0), T_1320)
+ node T_1322 = mux(T_880, UInt<2>(0), T_1321)
+ node T_1323 = mux(T_878, UInt<2>(0), T_1322)
+ node T_1324 = mux(T_876, UInt<2>(0), T_1323)
+ node T_1325 = mux(T_874, UInt<2>(0), T_1324)
+ node T_1326 = mux(T_872, UInt<2>(0), T_1325)
+ node T_1327 = mux(T_870, UInt<2>(0), T_1326)
+ node T_1328 = mux(T_868, UInt<2>(0), T_1327)
+ node T_1329 = mux(T_866, UInt<2>(0), T_1328)
+ node T_1330 = mux(T_864, UInt<2>(0), T_1329)
+ node T_1331 = mux(T_862, UInt<2>(0), T_1330)
+ node T_1332 = mux(T_860, UInt<2>(1), T_1331)
+ node T_1333 = mux(T_858, UInt<2>(1), T_1332)
+ node T_1334 = mux(T_856, UInt<2>(1), T_1333)
+ node T_1335 = mux(T_854, UInt<2>(1), T_1334)
+ node T_1336 = mux(T_852, UInt<2>(1), T_1335)
+ node T_1337 = mux(T_850, UInt<2>(0), T_1336)
+ node T_1338 = mux(T_848, UInt<2>(0), T_1337)
+ node T_1339 = mux(T_846, UInt<2>(0), T_1338)
+ node T_1340 = mux(T_844, UInt<2>(0), T_1339)
+ node T_1341 = mux(T_842, UInt<2>(0), T_1340)
+ node T_1342 = mux(T_840, UInt<2>(0), T_1341)
+ node T_1343 = mux(T_838, UInt<2>(2), T_1342)
+ node T_1344 = mux(T_836, UInt<2>(2), T_1343)
+ node T_1345 = mux(T_834, UInt<2>(0), T_1344)
+ node T_1346 = mux(T_832, UInt<2>(0), T_1345)
+ node T_1347 = mux(T_916, UInt<1>(0), UInt<1>(0))
+ node T_1348 = mux(T_914, UInt<1>(0), T_1347)
+ node T_1349 = mux(T_912, UInt<1>(0), T_1348)
+ node T_1350 = mux(T_910, UInt<1>(0), T_1349)
+ node T_1351 = mux(T_908, UInt<1>(0), T_1350)
+ node T_1352 = mux(T_906, UInt<1>(0), T_1351)
+ node T_1353 = mux(T_904, UInt<1>(1), T_1352)
+ node T_1354 = mux(T_902, UInt<1>(1), T_1353)
+ node T_1355 = mux(T_900, UInt<1>(1), T_1354)
+ node T_1356 = mux(T_898, UInt<1>(1), T_1355)
+ node T_1357 = mux(T_896, UInt<1>(1), T_1356)
+ node T_1358 = mux(T_894, UInt<1>(1), T_1357)
+ node T_1359 = mux(T_892, UInt<1>(1), T_1358)
+ node T_1360 = mux(T_890, UInt<1>(1), T_1359)
+ node T_1361 = mux(T_888, UInt<1>(1), T_1360)
+ node T_1362 = mux(T_886, UInt<1>(1), T_1361)
+ node T_1363 = mux(T_884, UInt<1>(1), T_1362)
+ node T_1364 = mux(T_882, UInt<1>(1), T_1363)
+ node T_1365 = mux(T_880, UInt<1>(1), T_1364)
+ node T_1366 = mux(T_878, UInt<1>(1), T_1365)
+ node T_1367 = mux(T_876, UInt<1>(1), T_1366)
+ node T_1368 = mux(T_874, UInt<1>(1), T_1367)
+ node T_1369 = mux(T_872, UInt<1>(1), T_1368)
+ node T_1370 = mux(T_870, UInt<1>(1), T_1369)
+ node T_1371 = mux(T_868, UInt<1>(1), T_1370)
+ node T_1372 = mux(T_866, UInt<1>(0), T_1371)
+ node T_1373 = mux(T_864, UInt<1>(0), T_1372)
+ node T_1374 = mux(T_862, UInt<1>(0), T_1373)
+ node T_1375 = mux(T_860, UInt<1>(1), T_1374)
+ node T_1376 = mux(T_858, UInt<1>(1), T_1375)
+ node T_1377 = mux(T_856, UInt<1>(1), T_1376)
+ node T_1378 = mux(T_854, UInt<1>(1), T_1377)
+ node T_1379 = mux(T_852, UInt<1>(1), T_1378)
+ node T_1380 = mux(T_850, UInt<1>(0), T_1379)
+ node T_1381 = mux(T_848, UInt<1>(0), T_1380)
+ node T_1382 = mux(T_846, UInt<1>(0), T_1381)
+ node T_1383 = mux(T_844, UInt<1>(0), T_1382)
+ node T_1384 = mux(T_842, UInt<1>(0), T_1383)
+ node T_1385 = mux(T_840, UInt<1>(0), T_1384)
+ node T_1386 = mux(T_838, UInt<1>(1), T_1385)
+ node T_1387 = mux(T_836, UInt<1>(1), T_1386)
+ node T_1388 = mux(T_834, UInt<1>(1), T_1387)
+ node T_1389 = mux(T_832, UInt<1>(1), T_1388)
+ node T_1390 = mux(T_916, UInt<2>(3), UInt<2>(0))
+ node T_1391 = mux(T_914, UInt<2>(2), T_1390)
+ node T_1392 = mux(T_912, UInt<2>(1), T_1391)
+ node T_1393 = mux(T_910, UInt<2>(3), T_1392)
+ node T_1394 = mux(T_908, UInt<2>(2), T_1393)
+ node T_1395 = mux(T_906, UInt<2>(1), T_1394)
+ node T_1396 = mux(T_904, UInt<2>(0), T_1395)
+ node T_1397 = mux(T_902, UInt<2>(0), T_1396)
+ node T_1398 = mux(T_900, UInt<2>(0), T_1397)
+ node T_1399 = mux(T_898, UInt<2>(0), T_1398)
+ node T_1400 = mux(T_896, UInt<2>(0), T_1399)
+ node T_1401 = mux(T_894, UInt<2>(0), T_1400)
+ node T_1402 = mux(T_892, UInt<2>(0), T_1401)
+ node T_1403 = mux(T_890, UInt<2>(0), T_1402)
+ node T_1404 = mux(T_888, UInt<2>(0), T_1403)
+ node T_1405 = mux(T_886, UInt<2>(0), T_1404)
+ node T_1406 = mux(T_884, UInt<2>(0), T_1405)
+ node T_1407 = mux(T_882, UInt<2>(0), T_1406)
+ node T_1408 = mux(T_880, UInt<2>(0), T_1407)
+ node T_1409 = mux(T_878, UInt<2>(0), T_1408)
+ node T_1410 = mux(T_876, UInt<2>(0), T_1409)
+ node T_1411 = mux(T_874, UInt<2>(0), T_1410)
+ node T_1412 = mux(T_872, UInt<2>(0), T_1411)
+ node T_1413 = mux(T_870, UInt<2>(0), T_1412)
+ node T_1414 = mux(T_868, UInt<2>(0), T_1413)
+ node T_1415 = mux(T_866, UInt<2>(0), T_1414)
+ node T_1416 = mux(T_864, UInt<2>(0), T_1415)
+ node T_1417 = mux(T_862, UInt<2>(0), T_1416)
+ node T_1418 = mux(T_860, UInt<2>(0), T_1417)
+ node T_1419 = mux(T_858, UInt<2>(0), T_1418)
+ node T_1420 = mux(T_856, UInt<2>(0), T_1419)
+ node T_1421 = mux(T_854, UInt<2>(0), T_1420)
+ node T_1422 = mux(T_852, UInt<2>(0), T_1421)
+ node T_1423 = mux(T_850, UInt<2>(0), T_1422)
+ node T_1424 = mux(T_848, UInt<2>(0), T_1423)
+ node T_1425 = mux(T_846, UInt<2>(0), T_1424)
+ node T_1426 = mux(T_844, UInt<2>(0), T_1425)
+ node T_1427 = mux(T_842, UInt<2>(0), T_1426)
+ node T_1428 = mux(T_840, UInt<2>(0), T_1427)
+ node T_1429 = mux(T_838, UInt<2>(0), T_1428)
+ node T_1430 = mux(T_836, UInt<2>(0), T_1429)
+ node T_1431 = mux(T_834, UInt<2>(0), T_1430)
+ node T_1432 = mux(T_832, UInt<2>(0), T_1431)
node rs1_addr = bits(ctrl.inst, 19, 15)
node rs2_addr = bits(ctrl.inst, 24, 20)
- reg st_type : UInt<2>
- reg ld_type : UInt<3>
- reg wb_sel : UInt<2>
- node T_2038 = bit(T_1994, 0)
- reg wb_en : UInt<1>
- reg csr_cmd : UInt<2>
- ctrl.pc_sel := T_1564
- node T_2039 = bit-not(ctrl.stall)
- node T_2040 = bit-not(ctrl.data_re)
- node T_2041 = bit-and(T_2039, T_2040)
- ctrl.inst_re := T_2041
- node T_2042 = neq(T_1908, UInt<3>(7))
- node T_2043 = bit(T_1822, 0)
- node T_2044 = bit-or(T_2042, T_2043)
- node T_2045 = mux(T_2044, UInt<1>(1), UInt<1>(0))
- ctrl.inst_type := T_2045
- ctrl.A_sel := T_1607
- ctrl.B_sel := T_1650
- ctrl.imm_sel := T_1693
- ctrl.alu_op := T_1736
- ctrl.br_type := T_1779
- ctrl.st_type := T_1865
- node T_2046 = bit-not(ctrl.stall)
- when T_2046 :
+ reg st_type : UInt<2>, clk, reset
+ reg ld_type : UInt<3>, clk, reset
+ reg wb_sel : UInt<2>, clk, reset
+ node T_1433 = bit(T_1389, 0)
+ reg wb_en : UInt<1>, clk, reset
+ reg csr_cmd : UInt<2>, clk, reset
+ ctrl.pc_sel := T_959
+ node T_1434 = not(ctrl.stall)
+ node T_1435 = not(ctrl.data_re)
+ node T_1436 = and(T_1434, T_1435)
+ ctrl.inst_re := T_1436
+ node T_1437 = neq(T_1303, UInt<3>(7))
+ node T_1438 = bit(T_1217, 0)
+ node T_1439 = or(T_1437, T_1438)
+ node T_1440 = mux(T_1439, UInt<1>(1), UInt<1>(0))
+ ctrl.inst_type := T_1440
+ ctrl.A_sel := T_1002
+ ctrl.B_sel := T_1045
+ ctrl.imm_sel := T_1088
+ ctrl.alu_op := T_1131
+ ctrl.br_type := T_1174
+ ctrl.st_type := T_1260
+ node T_1441 = not(ctrl.stall)
+ when T_1441 :
st_type := ctrl.st_type
- ld_type := T_1908
- wb_sel := T_1951
- node T_2047 = bit(T_1994, 0)
- wb_en := T_2047
- csr_cmd := T_2037
- node T_2048 = neq(ctrl.ld_type, UInt<3>(7))
- node T_2049 = neq(T_1908, UInt<3>(7))
- node T_2050 = mux(ctrl.stall, T_2048, T_2049)
- ctrl.data_re := T_2050
+ ld_type := T_1303
+ wb_sel := T_1346
+ node T_1442 = bit(T_1389, 0)
+ wb_en := T_1442
+ csr_cmd := T_1432
+ node T_1443 = neq(ctrl.ld_type, UInt<3>(7))
+ node T_1444 = neq(T_1303, UInt<3>(7))
+ node T_1445 = mux(ctrl.stall, T_1443, T_1444)
+ ctrl.data_re := T_1445
ctrl.ld_type := ld_type
ctrl.wb_en := wb_en
ctrl.wb_sel := wb_sel
diff --git a/test/chisel3/Datapath.fir b/test/chisel3/Datapath.fir
index c2752a37..1315041a 100644
--- a/test/chisel3/Datapath.fir
+++ b/test/chisel3/Datapath.fir
@@ -10,23 +10,23 @@ circuit Datapath :
input alu_op : UInt<4>
node shamt = bits(B, 4, 0)
- node T_433 = add-wrap(A, B)
- node T_434 = sub-wrap(A, B)
- node T_435 = as-SInt(A)
+ node T_433 = addw(A, B)
+ node T_434 = subw(A, B)
+ node T_435 = asSInt(A)
node T_436 = dshr(T_435, shamt)
- node T_437 = as-UInt(T_436)
+ node T_437 = asUInt(T_436)
node T_438 = dshr(A, shamt)
node T_439 = dshl(A, shamt)
node T_440 = bits(T_439, 31, 0)
- node T_441 = as-SInt(A)
- node T_442 = as-SInt(B)
+ node T_441 = asSInt(A)
+ node T_442 = asSInt(B)
node T_443 = lt(T_441, T_442)
- node T_444 = as-UInt(T_443)
+ node T_444 = asUInt(T_443)
node T_445 = lt(A, B)
- node T_446 = as-UInt(T_445)
- node T_447 = bit-and(A, B)
- node T_448 = bit-or(A, B)
- node T_449 = bit-xor(A, B)
+ node T_446 = asUInt(T_445)
+ node T_447 = and(A, B)
+ node T_448 = or(A, B)
+ node T_449 = xor(A, B)
node T_450 = eq(UInt<4>(10), alu_op)
node T_451 = mux(T_450, A, B)
node T_452 = eq(UInt<4>(4), alu_op)
@@ -52,9 +52,9 @@ circuit Datapath :
node T_471 = bits(oot, 31, 0)
out := T_471
node T_472 = bit(alu_op, 0)
- node T_473 = sub-wrap(UInt<1>(0), B)
+ node T_473 = subw(UInt<1>(0), B)
node T_474 = mux(T_472, T_473, B)
- node T_475 = add-wrap(A, T_474)
+ node T_475 = addw(A, T_474)
sum := T_475
module BrCond :
input rs1 : UInt<32>
@@ -63,32 +63,33 @@ circuit Datapath :
input br_type : UInt<3>
node eq = eq(rs1, rs2)
- node neq = bit-not(eq)
- node T_476 = as-SInt(rs1)
- node T_477 = as-SInt(rs2)
+ node neq = not(eq)
+ node T_476 = asSInt(rs1)
+ node T_477 = asSInt(rs2)
node lt = lt(T_476, T_477)
- node ge = bit-not(lt)
+ node ge = not(lt)
node ltu = lt(rs1, rs2)
- node geu = bit-not(ltu)
+ node geu = not(ltu)
node T_478 = eq(br_type, UInt<3>(2))
- node T_479 = bit-and(T_478, eq)
+ node T_479 = and(T_478, eq)
node T_480 = eq(br_type, UInt<3>(6))
- node T_481 = bit-and(T_480, neq)
- node T_482 = bit-or(T_479, T_481)
+ node T_481 = and(T_480, neq)
+ node T_482 = or(T_479, T_481)
node T_483 = eq(br_type, UInt<3>(1))
- node T_484 = bit-and(T_483, lt)
- node T_485 = bit-or(T_482, T_484)
+ node T_484 = and(T_483, lt)
+ node T_485 = or(T_482, T_484)
node T_486 = eq(br_type, UInt<3>(5))
- node T_487 = bit-and(T_486, ge)
- node T_488 = bit-or(T_485, T_487)
+ node T_487 = and(T_486, ge)
+ node T_488 = or(T_485, T_487)
node T_489 = eq(br_type, UInt<3>(0))
- node T_490 = bit-and(T_489, ltu)
- node T_491 = bit-or(T_488, T_490)
+ node T_490 = and(T_489, ltu)
+ node T_491 = or(T_488, T_490)
node T_492 = eq(br_type, UInt<3>(4))
- node T_493 = bit-and(T_492, geu)
- node T_494 = bit-or(T_491, T_493)
+ node T_493 = and(T_492, geu)
+ node T_494 = or(T_491, T_493)
taken := T_494
module RegFile :
+ input clk : Clock
input raddr1 : UInt<5>
input raddr2 : UInt<5>
output rdata1 : UInt<32>
@@ -97,20 +98,20 @@ circuit Datapath :
input waddr : UInt<5>
input wdata : UInt<32>
- cmem regs : UInt<32>[32]
+ cmem regs : UInt<32>[32], clk
node T_495 = eq(raddr1, UInt<1>(0))
- node T_496 = bit-not(T_495)
+ node T_496 = not(T_495)
infer accessor T_497 = regs[raddr1]
node T_498 = mux(T_496, T_497, UInt<1>(0))
rdata1 := T_498
node T_499 = eq(raddr2, UInt<1>(0))
- node T_500 = bit-not(T_499)
+ node T_500 = not(T_499)
infer accessor T_501 = regs[raddr2]
node T_502 = mux(T_500, T_501, UInt<1>(0))
rdata2 := T_502
node T_503 = eq(waddr, UInt<1>(0))
- node T_504 = bit-not(T_503)
- node T_505 = bit-and(wen, T_504)
+ node T_504 = not(T_503)
+ node T_505 = and(wen, T_504)
when T_505 :
infer accessor T_506 = regs[waddr]
T_506 := wdata
@@ -120,11 +121,11 @@ circuit Datapath :
input sel : UInt<3>
node T_507 = bits(inst, 31, 20)
- node Iimm = as-SInt(T_507)
+ node Iimm = asSInt(T_507)
node T_508 = bits(inst, 31, 25)
node T_509 = bits(inst, 11, 7)
node T_510 = cat(T_508, T_509)
- node Simm = as-SInt(T_510)
+ node Simm = asSInt(T_510)
node T_511 = bit(inst, 31)
node T_512 = bit(inst, 7)
node T_513 = bits(inst, 30, 25)
@@ -133,10 +134,10 @@ circuit Datapath :
node T_516 = cat(T_514, UInt<1>(0))
node T_517 = cat(T_513, T_516)
node T_518 = cat(T_515, T_517)
- node Bimm = as-SInt(T_518)
+ node Bimm = asSInt(T_518)
node T_519 = bits(inst, 31, 12)
node T_520 = cat(T_519, UInt<12>(0))
- node Uimm = as-SInt(T_520)
+ node Uimm = asSInt(T_520)
node T_521 = bit(inst, 31)
node T_522 = bits(inst, 19, 12)
node T_523 = bit(inst, 20)
@@ -147,10 +148,10 @@ circuit Datapath :
node T_528 = cat(T_525, UInt<1>(0))
node T_529 = cat(T_524, T_528)
node T_530 = cat(T_527, T_529)
- node Jimm = as-SInt(T_530)
+ node Jimm = asSInt(T_530)
node T_531 = bits(inst, 19, 15)
node T_532 = pad(T_531, 32)
- node Zimm = as-SInt(T_532)
+ node Zimm = asSInt(T_532)
node T_533 = eq(UInt<3>(3), sel)
node T_534 = mux(T_533, Jimm, Zimm)
node T_535 = eq(UInt<3>(2), sel)
@@ -161,19 +162,21 @@ circuit Datapath :
node T_540 = mux(T_539, Simm, T_538)
node T_541 = eq(UInt<3>(0), sel)
node T_542 = mux(T_541, Iimm, T_540)
- node T_543 = as-UInt(T_542)
+ node T_543 = asUInt(T_542)
out := T_543
module CSR :
+ input clk : Clock
+ input reset : UInt<1>
output host : {status : UInt<32>, tohost : UInt<32>, flip hid : UInt<1>}
input src : UInt<32>
input cmd : UInt<2>
output data : UInt<32>
input addr : UInt<12>
- reg reg_tohost : UInt<32>
- on-reset reg_tohost := UInt<32>(0)
- reg reg_status : UInt<32>
- on-reset reg_status := UInt<32>(0)
+ reg reg_tohost : UInt<32>, clk, reset
+ onreset reg_tohost := UInt<32>(0)
+ reg reg_status : UInt<32>, clk, reset
+ onreset reg_status := UInt<32>(0)
host.tohost := reg_tohost
host.status := reg_status
node T_544 = eq(UInt<12>(1291), addr)
@@ -191,33 +194,35 @@ circuit Datapath :
when T_552 : reg_status := src
node T_553 = eq(cmd, UInt<2>(2))
node T_554 = neq(src, UInt<1>(0))
- node T_555 = bit-and(T_553, T_554)
+ node T_555 = and(T_553, T_554)
when T_555 :
node T_556 = eq(addr, UInt<12>(1310))
when T_556 :
node T_557 = dshl(UInt<1>(1), bits(src,5,0))
- node T_558 = bit-or(data, T_557)
+ node T_558 = or(data, T_557)
reg_tohost := T_558
node T_559 = eq(addr, UInt<12>(1290))
when T_559 :
node T_560 = dshl(UInt<1>(1), bits(src,5,0))
- node T_561 = bit-or(data, T_560)
+ node T_561 = or(data, T_560)
reg_status := T_561
node T_562 = eq(cmd, UInt<2>(3))
node T_563 = neq(src, UInt<1>(0))
- node T_564 = bit-and(T_562, T_563)
+ node T_564 = and(T_562, T_563)
when T_564 :
node T_565 = eq(addr, UInt<12>(1310))
when T_565 :
node T_566 = dshl(UInt<1>(0), bits(src,5,0))
- node T_567 = bit-and(data, T_566)
+ node T_567 = and(data, T_566)
reg_tohost := T_567
node T_568 = eq(addr, UInt<12>(1290))
when T_568 :
node T_569 = dshl(UInt<1>(0), bits(src,5,0))
- node T_570 = bit-and(data, T_569)
+ node T_570 = and(data, T_569)
reg_status := T_570
module Datapath :
+ input clk : Clock
+ input reset : UInt<1>
output host : {status : UInt<32>, tohost : UInt<32>, flip hid : UInt<1>}
input ctrl : {flip inst : UInt<32>, pc_sel : UInt<1>, inst_type : UInt<1>, inst_re : UInt<1>, flip stall : UInt<1>, imm_sel : UInt<3>, wb_en : UInt<1>, wb_sel : UInt<2>, A_sel : UInt<1>, B_sel : UInt<1>, alu_op : UInt<4>, br_type : UInt<3>, data_re : UInt<1>, st_type : UInt<2>, ld_type : UInt<3>, csr_cmd : UInt<2>}
output icache : {re : UInt<1>, flip dout : UInt<32>, we : UInt<4>, addr : UInt<32>, din : UInt<32>}
@@ -227,35 +232,36 @@ circuit Datapath :
inst alu of ALU
inst brCond of BrCond
inst regFile of RegFile
+ regFile.clk := clk
inst immGen of ImmGenWire
- reg fe_inst : UInt<32>
- on-reset fe_inst := UInt<32>(0)
- reg fe_pc : UInt
- reg ew_inst : UInt<32>
- on-reset ew_inst := UInt<32>(0)
- reg ew_pc : UInt
- reg ew_alu : UInt
- node T_571 = sub-wrap(UInt<14>(8192), UInt<32>(4))
- reg pc : UInt<32>
- on-reset pc := T_571
+ reg fe_inst : UInt<32>, clk, reset
+ onreset fe_inst := UInt<32>(0)
+ reg fe_pc : UInt, clk, reset
+ reg ew_inst : UInt<32>, clk, reset
+ onreset ew_inst := UInt<32>(0)
+ reg ew_pc : UInt, clk, reset
+ reg ew_alu : UInt, clk, reset
+ node T_571 = subw(UInt<14>(8192), UInt<32>(4))
+ reg pc : UInt<32>, clk, reset
+ onreset pc := T_571
node T_572 = eq(ctrl.pc_sel, UInt<1>(1))
- node T_573 = bit-or(T_572, brCond.taken)
- node T_574 = add-wrap(pc, UInt<3>(4))
+ node T_573 = or(T_572, brCond.taken)
+ node T_574 = addw(pc, UInt<3>(4))
node iaddr = mux(T_573, alu.sum, T_574)
node T_575 = eq(ctrl.inst_type, UInt<1>(1))
- node T_576 = bit-or(T_575, brCond.taken)
+ node T_576 = or(T_575, brCond.taken)
node inst = mux(T_576, UInt<32>(19), icache.dout)
icache.we := UInt<1>(0)
icache.din := UInt<1>(0)
icache.addr := iaddr
icache.re := ctrl.inst_re
node T_577 = eq(dcache.we, UInt<1>(0))
- node T_578 = bit-not(T_577)
- node T_579 = bit-not(T_578)
- node T_580 = bit-and(icache.re, T_579)
+ node T_578 = not(T_577)
+ node T_579 = not(T_578)
+ node T_580 = and(icache.re, T_579)
node T_581 = mux(T_580, iaddr, pc)
pc := T_581
- node T_582 = bit-not(stall)
+ node T_582 = not(stall)
when T_582 :
fe_pc := pc
fe_inst := inst
@@ -269,19 +275,19 @@ circuit Datapath :
immGen.inst := fe_inst
immGen.sel := ctrl.imm_sel
node T_583 = eq(rs1_addr, UInt<1>(0))
- node rs1NotZero = bit-not(T_583)
+ node rs1NotZero = not(T_583)
node T_584 = eq(rs2_addr, UInt<1>(0))
- node rs2NotZero = bit-not(T_584)
+ node rs2NotZero = not(T_584)
node T_585 = eq(ctrl.wb_sel, UInt<2>(0))
- node alutype = bit-and(ctrl.wb_en, T_585)
+ node alutype = and(ctrl.wb_en, T_585)
node ex_rd_addr = bits(ew_inst, 11, 7)
- node T_586 = bit-and(alutype, rs1NotZero)
+ node T_586 = and(alutype, rs1NotZero)
node T_587 = eq(rs1_addr, ex_rd_addr)
- node T_588 = bit-and(T_586, T_587)
+ node T_588 = and(T_586, T_587)
node rs1 = mux(T_588, ew_alu, regFile.rdata1)
- node T_589 = bit-and(alutype, rs2NotZero)
+ node T_589 = and(alutype, rs2NotZero)
node T_590 = eq(rs2_addr, ex_rd_addr)
- node T_591 = bit-and(T_589, T_590)
+ node T_591 = and(T_589, T_590)
node rs2 = mux(T_591, ew_alu, regFile.rdata2)
node T_592 = eq(ctrl.A_sel, UInt<1>(0))
node T_593 = mux(T_592, rs1, fe_pc)
@@ -297,7 +303,7 @@ circuit Datapath :
node T_597 = dshl(T_596, UInt<3>(4))
node T_598 = bit(alu.sum, 0)
node T_599 = dshl(T_598, UInt<2>(3))
- node woffset = bit-or(T_597, T_599)
+ node woffset = or(T_597, T_599)
dcache.re := ctrl.data_re
node T_600 = mux(stall, ew_alu, alu.sum)
dcache.addr := T_600
@@ -318,7 +324,7 @@ circuit Datapath :
node T_614 = dshl(rs2, woffset)
node T_615 = bits(T_614, 31, 0)
dcache.din := T_615
- node T_616 = bit-not(stall)
+ node T_616 = not(stall)
when T_616 :
ew_pc := fe_pc
ew_inst := fe_inst
@@ -327,16 +333,16 @@ circuit Datapath :
node T_618 = dshl(T_617, UInt<3>(4))
node T_619 = bit(ew_alu, 0)
node T_620 = dshl(T_619, UInt<2>(3))
- node loffset = bit-or(T_618, T_620)
+ node loffset = or(T_618, T_620)
node lshift = dshr(dcache.dout, loffset)
node T_621 = bits(lshift, 15, 0)
- node T_622 = as-SInt(T_621)
+ node T_622 = asSInt(T_621)
node T_623 = pad(T_622, 32)
- node T_624 = as-UInt(T_623)
+ node T_624 = asUInt(T_623)
node T_625 = bits(lshift, 7, 0)
- node T_626 = as-SInt(T_625)
+ node T_626 = asSInt(T_625)
node T_627 = pad(T_626, 32)
- node T_628 = as-UInt(T_627)
+ node T_628 = asUInt(T_627)
node T_629 = bits(lshift, 15, 0)
node T_630 = bits(lshift, 7, 0)
node T_631 = eq(UInt<3>(4), ctrl.ld_type)
@@ -348,12 +354,14 @@ circuit Datapath :
node T_637 = eq(UInt<3>(1), ctrl.ld_type)
node load = mux(T_637, T_624, T_636)
inst csr of CSR
+ csr.reset := reset
+ csr.clk := clk
host := csr.host
csr.src := ew_alu
node T_638 = bits(ew_inst, 31, 20)
csr.addr := T_638
csr.cmd := ctrl.csr_cmd
- node T_639 = add-wrap(ew_pc, UInt<3>(4))
+ node T_639 = addw(ew_pc, UInt<3>(4))
node T_640 = eq(UInt<2>(3), ctrl.wb_sel)
node T_641 = mux(T_640, csr.data, ew_alu)
node T_642 = eq(UInt<2>(2), ctrl.wb_sel)
diff --git a/test/features/SeqMem.fir b/test/features/SeqMem.fir
index 4b346ea9..4714ad4f 100644
--- a/test/features/SeqMem.fir
+++ b/test/features/SeqMem.fir
@@ -2,6 +2,7 @@
;CHECK: Done!
circuit Top :
module Top :
+ input clk : Clock
wire i : UInt<5>
i := UInt(1)
wire i0 : UInt<5>
@@ -9,14 +10,14 @@ circuit Top :
i0 := UInt(10)
- cmem m-com : UInt<128>[32]
+ cmem m-com : UInt<128>[32], clk
infer accessor r-com = m-com[i]
infer accessor w-com = m-com[i]
j := r-com
w-com := j
- smem m-seq : UInt<128>[32]
+ smem m-seq : UInt<128>[32], clk
infer accessor r-seq = m-seq[i]
infer accessor w-seq = m-seq[i]
j := r-seq
diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir
index 0daec379..660ce77e 100644
--- a/test/passes/expand-accessors/accessor-mem.fir
+++ b/test/passes/expand-accessors/accessor-mem.fir
@@ -3,7 +3,8 @@
;CHECK: Expand Accessors
circuit top :
module top :
- cmem m : UInt<32>[2][2][2]
+ input clk : Clock
+ cmem m : UInt<32>[2][2][2], clk
wire i : UInt<4>
i := UInt(1)
infer accessor a = m[i] ;CHECK: read accessor a = m[i]
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 13:37:32 +0000