Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass

1 files changed, 21 insertions, 0 deletions

diff --git a/test/features/TwoClocks.fir b/test/features/TwoClocks.fir
new file mode 100644
index 00000000..cbbb01f1
--- /dev/null
+++ b/test/features/TwoClocks.fir
@@ -0,0 +1,21 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+circuit Top : 
+  module Top : 
+    input clk1 : Clock
+    input clk2 : Clock
+    input reset1 : UInt<1>
+    input reset2 : UInt<1>
+    reg src : UInt<10>, clk1, reset1
+    reg sink : UInt<10>, clk2, reset2
+
+    onreset src := UInt(0)
+    src := addw(src,UInt(1))
+
+    reg sync_A : UInt<10>, clk2, reset2
+    sync_A := src
+    reg sync_B : UInt<10>, clk2, reset2
+    sync_B := sync_A
+
+    sink := sync_B
+
+;CHECK: Done!