Added isinvalid and validif

5 files changed, 147 insertions, 0 deletions

diff --git a/test/features/IsInvalid.fir b/test/features/IsInvalid.fir
new file mode 100644
index 00000000..fbb69ef7
--- /dev/null
+++ b/test/features/IsInvalid.fir
@@ -0,0 +1,74 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+circuit Top : 
+  module Top : 
+    input clk : Clock
+    input reset : UInt<1>
+    input a : { w : UInt<42>, flip x : UInt<30>}[2]
+    output b : { w : UInt<42>, flip x : UInt<30>}[2]
+    mem m : 
+       depth => 10
+       data-type => UInt<32>[4]
+       read-latency => 0
+       write-latency => 1
+       reader => r
+       writer => w
+       read-writer => rw
+    wire x : { w : UInt<42>, x : UInt<20>}
+    reg c : { w : UInt<42>, x : UInt<20>},clk,reset,x
+    inst other of Other
+   
+    clk is invalid
+    reset is invalid
+    a is invalid
+    b is invalid
+    m is invalid
+    x is invalid
+    c is invalid
+    other is invalid
+  module Other :
+    input a : { w : UInt<42>, flip x : UInt<30>}
+    output b : { w : UInt<42>, flip x : UInt<30>}
+    b <= a
+
+
+;CHECK: Expand Connects
+;CHECK: skip
+;CHECK: skip
+;CHECK: a[0].x is invalid
+;CHECK: a[1].x is invalid
+;CHECK: b[0].w is invalid
+;CHECK: b[1].w is invalid
+;CHECK: m.r.addr is invalid
+;CHECK: m.r.en is invalid
+;CHECK: m.r.clk is invalid
+;CHECK: m.w.data[0] is invalid
+;CHECK: m.w.data[1] is invalid
+;CHECK: m.w.data[2] is invalid
+;CHECK: m.w.data[3] is invalid
+;CHECK: m.w.mask[0] is invalid
+;CHECK: m.w.mask[1] is invalid
+;CHECK: m.w.mask[2] is invalid
+;CHECK: m.w.mask[3] is invalid
+;CHECK: m.w.addr is invalid
+;CHECK: m.w.en is invalid
+;CHECK: m.w.clk is invalid
+;CHECK: m.rw.wdata[0] is invalid
+;CHECK: m.rw.wdata[1] is invalid
+;CHECK: m.rw.wdata[2] is invalid
+;CHECK: m.rw.wdata[3] is invalid
+;CHECK: m.rw.wmask[0] is invalid
+;CHECK: m.rw.wmask[1] is invalid
+;CHECK: m.rw.wmask[2] is invalid
+;CHECK: m.rw.wmask[3] is invalid
+;CHECK: m.rw.waddr is invalid
+;CHECK: m.rw.wen is invalid
+;CHECK: m.rw.raddr is invalid
+;CHECK: m.rw.ren is invalid
+;CHECK: m.rw.clk is invalid
+;CHECK: x.w is invalid
+;CHECK: x.x is invalid
+;CHECK: c.w is invalid
+;CHECK: c.x is invalid
+;CHECK: other.a.w is invalid
+;CHECK: other.b.x is invalid   
+;CHECK: Done!
diff --git a/test/features/MuxNodeExamples.fir b/test/features/MuxNodeExamples.fir
new file mode 100644
index 00000000..07fa16b4
--- /dev/null
+++ b/test/features/MuxNodeExamples.fir
@@ -0,0 +1,28 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+;CHECK: Expand Connects
+circuit Top : 
+  module Top : 
+    input a : {f:UInt<3>[3], flip g:UInt<3>[3]}[2]
+    input b : {f:UInt<3>[3], flip g:UInt<3>[3]}[2]
+    input p : UInt<1>
+    input i : UInt<1>
+    b[0].g[0] <= UInt(0)
+    b[0].g[1] <= UInt(0)
+    b[0].g[2] <= UInt(0)
+    b[1].g[0] <= UInt(0)
+    b[1].g[1] <= UInt(0)
+    b[1].g[2] <= UInt(0)
+    a[0].g[0] <= UInt(0)
+    a[0].g[1] <= UInt(0)
+    a[0].g[2] <= UInt(0)
+    a[1].g[0] <= UInt(0)
+    a[1].g[1] <= UInt(0)
+    a[1].g[2] <= UInt(0)
+    node x = mux(p,a[i].f,b[i].f)
+
+
+
+;CHECK: Finished Expand Connects
+;CHECK: Done!
+
+
diff --git a/test/features/MuxType.fir b/test/features/MuxType.fir
new file mode 100644
index 00000000..b0e7e7ef
--- /dev/null
+++ b/test/features/MuxType.fir
@@ -0,0 +1,12 @@
+
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+;CHECK: Expand Connects
+circuit Top : 
+  module Top : 
+    input a: UInt<1>
+    input b: UInt<32>
+    input p : UInt<1>
+    output d: UInt
+    node y = mux(p, a, b)
+    d <= y
+;CHECK:Done!
diff --git a/test/features/NodeBundle.fir b/test/features/NodeBundle.fir
new file mode 100644
index 00000000..c4c33107
--- /dev/null
+++ b/test/features/NodeBundle.fir
@@ -0,0 +1,12 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+;CHECK: Lower Types
+circuit Top : 
+  module Top : 
+    input a: {w:UInt<42>,x:UInt<20>}
+    node d = a
+;CHECK: node d_w = a_w
+;CHECK: node d_x = a_x
+
+;CHECK: Finished Lower Types
+;CHECK: Done!
+
diff --git a/test/features/ValidIf.fir b/test/features/ValidIf.fir
new file mode 100644
index 00000000..70c69313
--- /dev/null
+++ b/test/features/ValidIf.fir
@@ -0,0 +1,21 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+circuit Top : 
+  module Top : 
+    input clk : Clock
+    input reset : UInt<1>
+    input a : { w : UInt<42>, x : UInt<30>}[2]
+    input b : { w : UInt<42>, x : UInt<30>}[2]
+    input p: UInt<1>
+    input q: UInt<1>
+    output c : { w : UInt<42>, x : UInt<30>}[2]
+    output d : { w : UInt<42>, x : UInt<30>}[2]
+    
+    c is invalid
+    when p :
+       when q :
+          c <= a
+       else :
+          c <= b
+    d <= validif(p,b)
+
+;CHECK: Done!