diff options
| author | azidar | 2015-07-31 16:31:10 -0700 |
|---|---|---|
| committer | azidar | 2015-07-31 16:31:10 -0700 |
| commit | ba55a55ee07805d28995b535beb5a19bd4a99c5c (patch) | |
| tree | bc636b7f11efb34166a357678a1b4c2471f33552 /test/features | |
| parent | 0fc3314eb15c6f2e42b21a175978a69217810879 (diff) | |
Added errors for bulk connects where field names match but types/flips don't
Diffstat (limited to 'test/features')
| -rw-r--r-- | test/features/BulkConnect.fir | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/test/features/BulkConnect.fir b/test/features/BulkConnect.fir index bf5b330e..9120c4a8 100644 --- a/test/features/BulkConnect.fir +++ b/test/features/BulkConnect.fir @@ -2,18 +2,14 @@ ;CHECK: Lower To Ground circuit Top : module Top : - wire a : { w : UInt<42>, x : UInt<10>, flip y : UInt<42>, z : SInt<42>} + wire a : { w : UInt<42>} a.w := UInt(1) - a.y := UInt(1) - a.z := SInt(1) - wire b : { w : UInt<42>, x : UInt<20>, y : UInt<42>, z : UInt<42>} + wire b : { w : UInt<42>, x : UInt<20>} b.w := UInt(1) b.x := UInt(1) - b.y := UInt(1) - b.z := UInt(1) a <> b ; CHECK: a$w := b$w - ; CHECK: a$x := b$x + ; CHECK-NOT: a$x := b$x ; CHECK-NOT: a$y := b$y ; CHECK-NOT: b$y := a$y ; CHECK-NOT: a$z := b$z |