Added errors for bulk connects where field names match but types/flips don't

4 files changed, 56 insertions, 9 deletions

diff --git a/TODO b/TODO
index 348197b8..030634d4 100644
--- a/TODO
+++ b/TODO
@@ -8,6 +8,7 @@ put clocks on accessors
 add clock check to high firrtl check
 registers in onreset cannot have flips
 add equivalence to spec
+remove SInt from bit/bits in spec
 
 Tests:
    Lowering for instance types with bundle ports
diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza
index 8727f762..f97b43b7 100644
--- a/src/main/stanza/errors.stanza
+++ b/src/main/stanza/errors.stanza
@@ -621,13 +621,31 @@ public defn check-types (c:Circuit) -> Circuit :
          (e:DoPrim) : check-types-primop(e,errors,info)
          (e:UIntValue|SIntValue) : false
       e
+
+   defn bulk-equals? (t1:Type,t2:Type) -> True|False :
+      match(t1,t2) :
+         (t1:BundleType,t2:BundleType) : 
+            var same? = true
+            for (f1 in fields(t1),f2 in fields(t2)) do :
+               if name(f1) == name(f2) : 
+                  if flip(f1) != flip(f2) : same? = false
+                  if not bulk-equals?(type(f1),type(f2)) : same? = false
+            same?
+         (t1:ClockType,t2:ClockType) : true
+         (t1:UIntType,t2:UIntType) : true
+         (t1:SIntType,t2:SIntType) : true
+         (t1:VectorType,t2:VectorType) :
+            if bulk-equals?(type(t1),type(t2)) : true
+            else : false
+         (t1,t2) : false
+        
    defn check-types-s (s:Stmt) -> Stmt :
       map{check-types-s,_} $ {
          match(map(check-types-e{info(s),_},s)) : 
             (s:Connect) : 
                if type(loc(s)) != type(exp(s)) : add(errors,InvalidConnect(info(s)))
-            (s:Connect) : 
-               if type(loc(s)) != type(exp(s)) : add(errors,InvalidConnect(info(s)))
+            (s:BulkConnect) : 
+               if not bulk-equals?(type(loc(s)),type(exp(s))) : add(errors,InvalidConnect(info(s)))
             (s:OnReset) : 
                if type(loc(s)) != type(exp(s)) : add(errors,InvalidConnect(info(s)))
             (s:Conditionally) :
diff --git a/test/errors/type/BulkConnect.fir b/test/errors/type/BulkConnect.fir
new file mode 100644
index 00000000..da62ef4d
--- /dev/null
+++ b/test/errors/type/BulkConnect.fir
@@ -0,0 +1,32 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
+;CHECK: BulkConnect.fir@10.4: [module Top]  Type mismatch.
+;CHECK: BulkConnect.fir@14.4: [module Top]  Type mismatch.
+;CHECK: BulkConnect.fir@26.4: [module Top]  Type mismatch.
+;CHECK: BulkConnect.fir@30.4: [module Top]  Type mismatch.
+circuit Top : 
+  module Top : 
+    wire a : { w : UInt<42>}
+    wire b : { w : SInt<42>}
+    a <> b 
+
+    wire c : { w : UInt<10>}
+    wire d : { flip w : UInt<12> }
+    c <> d
+
+    wire e : { w : UInt<10>}
+    wire f : { x : UInt<12> }
+    e <> f
+
+    wire g : { w : { y : UInt<10> }}
+    wire h : { w : { x : UInt<12> }}
+    g <> h
+
+    wire i : { w : { flip y : UInt<10> }}
+    wire j : { w : { y : UInt<12> }}
+    i <> j
+
+    wire k : { w : { y : SInt<10> }}
+    wire l : { w : { y : UInt<12> }}
+    k <> l
+
+
diff --git a/test/features/BulkConnect.fir b/test/features/BulkConnect.fir
index bf5b330e..9120c4a8 100644
--- a/test/features/BulkConnect.fir
+++ b/test/features/BulkConnect.fir
@@ -2,18 +2,14 @@
 ;CHECK: Lower To Ground
 circuit Top : 
   module Top : 
-    wire a : { w : UInt<42>, x : UInt<10>, flip y : UInt<42>, z : SInt<42>}
+    wire a : { w : UInt<42>}
     a.w := UInt(1)
-    a.y := UInt(1)
-    a.z := SInt(1)
-    wire b : { w : UInt<42>, x : UInt<20>, y : UInt<42>, z : UInt<42>}
+    wire b : { w : UInt<42>, x : UInt<20>}
     b.w := UInt(1)
     b.x := UInt(1)
-    b.y := UInt(1)
-    b.z := UInt(1)
     a <> b 
     ; CHECK:     a$w := b$w
-    ; CHECK:     a$x := b$x
+    ; CHECK-NOT: a$x := b$x
     ; CHECK-NOT: a$y := b$y
     ; CHECK-NOT: b$y := a$y
     ; CHECK-NOT: a$z := b$z