New memory works with verilog. Slowly changing tests and fixing bugs.

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

13 files changed, 106 insertions, 83 deletions

diff --git a/test/features/BigInt.fir b/test/features/BigInt.fir
index 225f1d8b..a8dadcfc 100644
--- a/test/features/BigInt.fir
+++ b/test/features/BigInt.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s
 circuit Top : 
   module Top : 
     node x = UInt("h2")
diff --git a/test/features/BulkConnect.fir b/test/features/BulkConnect.fir
index f08d6dc7..a57ce199 100644
--- a/test/features/BulkConnect.fir
+++ b/test/features/BulkConnect.fir
@@ -1,39 +1,39 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-;CHECK: Lower To Ground
+;CHECK: Expand Connects
 circuit Top : 
   module Top : 
     wire a : { w : UInt<42>}
-    a.w := UInt(1)
+    a.w <= UInt(1)
     wire b : { w : UInt<42>, x : UInt<20>}
-    b.w := UInt(1)
-    b.x := UInt(1)
-    a <> b 
-    ; CHECK:     a$w := b$w
-    ; CHECK-NOT: a$x := b$x
-    ; CHECK-NOT: a$y := b$y
-    ; CHECK-NOT: b$y := a$y
-    ; CHECK-NOT: a$z := b$z
+    b.w <= UInt(1)
+    b.x <= UInt(1)
+    a <- b 
+    ; CHECK:     a.w <= b.w
+    ; CHECK-NOT: a.x <= b.x
+    ; CHECK-NOT: a.y <= b.y
+    ; CHECK-NOT: b.y <= a.y
+    ; CHECK-NOT: a.z <= b.z
     
 
     wire c : { x : { y : UInt<1>, z : UInt<1>}}[4]
-    c[0].x.z := UInt(1)
-    c[1].x.z := UInt(1)
-    c[2].x.y := UInt(1)
-    c[2].x.z := UInt(1)
-    c[3].x.y := UInt(1)
-    c[3].x.z := UInt(1)
+    c[0].x.z <= UInt(1)
+    c[1].x.z <= UInt(1)
+    c[2].x.y <= UInt(1)
+    c[2].x.z <= UInt(1)
+    c[3].x.y <= UInt(1)
+    c[3].x.z <= UInt(1)
     wire d : { x : { y : UInt<1>}}[2]
-    d[0].x.y := UInt(1)
-    d[1].x.y := UInt(1)
-    c <> d
-    ; CHECK:     c$0$x$y := d$0$x$y
-    ; CHECK:     c$1$x$y := d$1$x$y
-    ; CHECK-NOT: c$2$x$y := d$2$x$y
-    ; CHECK-NOT: c$3$x$y := d$3$x$y
-    ; CHECK-NOT: c$0$x$z := d$0$x$z
-    ; CHECK-NOT: c$1$x$z := d$1$x$z
-    ; CHECK-NOT: c$2$x$z := d$2$x$z
-    ; CHECK-NOT: c$3$x$z := d$3$x$z
+    d[0].x.y <= UInt(1)
+    d[1].x.y <= UInt(1)
+    c <- d
+    ; CHECK:     c[0].x.y <= d[0].x.y
+    ; CHECK:     c[1].x.y <= d[1].x.y
+    ; CHECK-NOT: c[2].x.y <= d[2].x.y
+    ; CHECK-NOT: c[3].x.y <= d[3].x.y
+    ; CHECK-NOT: c[0].x.z <= d[0].x.z
+    ; CHECK-NOT: c[1].x.z <= d[1].x.z
+    ; CHECK-NOT: c[2].x.z <= d[2].x.z
+    ; CHECK-NOT: c[3].x.z <= d[3].x.z
 
-;CHECK: Finished Lower To Ground
+;CHECK: Finished Expand Connects
 ;CHECK: Done!
diff --git a/test/features/CondRead.fir b/test/features/CondRead.fir
index a9ae27ca..5dd1d321 100644
--- a/test/features/CondRead.fir
+++ b/test/features/CondRead.fir
@@ -12,7 +12,7 @@ circuit CondRead :
     poison xxx : UInt<6>
     wire data : UInt<20>
     read accessor readport = mem[mux(pred,index,xxx)]
-    out := readport
+    out <= readport
 
 
 ; CHECK: read accessor readport = mem[mux(pred,index,index_0)]
diff --git a/test/features/ExModule.fir b/test/features/ExModule.fir
index 146d11b9..b31c77c9 100644
--- a/test/features/ExModule.fir
+++ b/test/features/ExModule.fir
@@ -3,9 +3,9 @@ circuit Top :
   module Top : 
     output z : UInt<4>
     inst i of BlackBox
-    i.x := UInt(1)
-    i.y := UInt(2)
-    z := i.z
+    i.x <= UInt(1)
+    i.y <= UInt(2)
+    z <= i.z
   extmodule BlackBox :
     input x : UInt<4>
     input y : UInt<4>
diff --git a/test/features/InitAccessor.fir b/test/features/InitAccessor.fir
index 0bf861f2..356b5a68 100644
--- a/test/features/InitAccessor.fir
+++ b/test/features/InitAccessor.fir
@@ -5,10 +5,10 @@ circuit Top :
    module Top :
       input in : UInt<1>
       wire b : UInt<1>[3]
-      b.0 := UInt(1)
-      b.1 := UInt(1)
-      b.2 := UInt(1)
+      b.0 <= UInt(1)
+      b.1 <= UInt(1)
+      b.2 <= UInt(1)
       node c = UInt(1)
       infer accessor a = b[c]
       when in : 
-         a := UInt(1)
+         a <= UInt(1)
diff --git a/test/features/InitializeVec.fir b/test/features/InitializeVec.fir
index 0aa28835..ef6400a0 100644
--- a/test/features/InitializeVec.fir
+++ b/test/features/InitializeVec.fir
@@ -6,17 +6,17 @@ circuit Tst :
     input in : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>}
     output outs : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>}[4]
     
-    in.ready := UInt<1>(1)
-    outs[0].valid := UInt<1>(0)
-    outs[0].bits := UInt<1>(0)
-    outs[1].valid := UInt<1>(0)
-    outs[1].bits := UInt<1>(0)
-    outs[2].valid := UInt<1>(0)
-    outs[2].bits := UInt<1>(0)
-    outs[3].valid := UInt<1>(0)
-    outs[3].bits := UInt<1>(0)
-    in.ready := UInt<1>(1)
+    in.ready <= UInt<1>(1)
+    outs[0].valid <= UInt<1>(0)
+    outs[0].bits <= UInt<1>(0)
+    outs[1].valid <= UInt<1>(0)
+    outs[1].bits <= UInt<1>(0)
+    outs[2].valid <= UInt<1>(0)
+    outs[2].bits <= UInt<1>(0)
+    outs[3].valid <= UInt<1>(0)
+    outs[3].bits <= UInt<1>(0)
+    in.ready <= UInt<1>(1)
     infer accessor out = outs[in.bits]
     when out.ready : 
-      out.bits := UInt<7>(99)
-      out.valid := UInt<1>(1)
+      out.bits <= UInt<7>(99)
+      out.valid <= UInt<1>(1)
diff --git a/test/features/Link.fir b/test/features/Link.fir
index 040ac2c5..57fb8605 100644
--- a/test/features/Link.fir
+++ b/test/features/Link.fir
@@ -1,5 +1,5 @@
 ; RUN: firrtl -i %s -m %S/Queue.fir -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-;CHECK: Lower To Ground
+;CHECK: Done!
 circuit Top : 
   module Top : 
     input clk : Clock
@@ -7,8 +7,8 @@ circuit Top :
     output out : UInt<10>
     
     inst q of Queue
-    q.clk := clk
-    q.reset := reset
-    q.in := UInt(1)
-    out := q.out
+    q.clk <= clk
+    q.reset <= reset
+    q.in <= UInt(1)
+    out <= q.out
 
diff --git a/test/features/Long.fir b/test/features/Long.fir
index b191ac55..7ac5ad6c 100644
--- a/test/features/Long.fir
+++ b/test/features/Long.fir
@@ -3,4 +3,4 @@
 circuit Top : 
   module Top : 
     wire a : UInt
-    a := UInt("h4261441663")
+    a <= UInt("h4261441663")
diff --git a/test/features/Poison.fir b/test/features/Poison.fir
index d8aa4411..2b47411f 100644
--- a/test/features/Poison.fir
+++ b/test/features/Poison.fir
@@ -5,14 +5,36 @@ circuit Poison :
     input clk : Clock
     input reset : UInt<1>
     input index : UInt<7>
+    input wmask : {x:UInt<1>, y:UInt<1>}
     input p : UInt<1>
     output out : {x : UInt<10>, y : UInt<10>}
-     
     poison q : {x : UInt<10>, y : UInt<10>}
-    smem m : {x : UInt<10>, y : UInt<10>}[128],clk
-    infer accessor r = m[index]
+    mem m : 
+       data-type => {x : UInt<10>, y : UInt<10>}
+       depth => 128
+       read-latency => 1
+       write-latency => 2
+       reader => r
+       writer => w
+       read-writer => rw
+    m.r.addr <= index
+    m.r.en <= UInt(1)
+    m.r.clk <= clk
+    m.w.addr <= index
+    m.w.en <= UInt(1)
+    m.w.mask <= wmask
+    m.w.clk <= clk
+    m.w.data <= q
+
+    m.rw.clk <= clk
+    m.rw.raddr <= index
+    m.rw.ren <= UInt(1)
+    m.rw.waddr <= index
+    m.rw.wen <= UInt(1)
+    m.rw.wmask <= wmask
+    m.rw.wdata <= q
     when p : 
-      out := r
+      out <= m.r.data
     else :
-      out := q
+      out <= q
 
diff --git a/test/features/Printf.fir b/test/features/Printf.fir
index 2f8dc985..4e8682ff 100644
--- a/test/features/Printf.fir
+++ b/test/features/Printf.fir
@@ -1,20 +1,21 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
 
-;CHECK: Lower To Ground
+;CHECK: Expand Whens
 circuit Top : 
   module Top : 
     input x : {y : UInt<1>}
     input p : UInt<1>
     input clk : Clock
-    printf(clk,"Hello World!\n")
-    printf(clk,"Hello World! %x\n", x.y)
+    input en : UInt<1>
+    printf(clk,en,"Hello World!\n")
+    printf(clk,en,"Hello World! %x\n", x.y)
     when p :
-       printf(clk,"In consequence\n")
+       printf(clk,en,"In consequence\n")
     else :
-       printf(clk,"In alternate\n")
+       printf(clk,en,"In alternate\n")
 
-;CHECK: printf(clk, "Hello World!\n")
-;CHECK: printf(clk, "Hello World! %x\n", x$y)
-;CHECK: when p : printf(clk, "In consequence\n")
-;CHECK: when not(p) : printf(clk, "In alternate\n")   
+;CHECK: printf(clk, en, "Hello World!\n")
+;CHECK: printf(clk, en, "Hello World! %x\n", x.y)
+;CHECK: printf(clk, and(p, en), "In consequence\n")
+;CHECK: printf(clk, and(eqv(p, UInt("h0")), en), "In alternate\n")   
 ;CHECK: Done!
diff --git a/test/features/Queue.fir b/test/features/Queue.fir
index 07132d94..9b19caf4 100644
--- a/test/features/Queue.fir
+++ b/test/features/Queue.fir
@@ -7,6 +7,6 @@ circuit Queue :
     input clk : Clock
     input reset : UInt<1>
   
-    reg r : UInt<10>,clk,reset
-    r := in
-    out := r
+    reg r : UInt<10>,clk,reset,in
+    r <= in
+    out <= r
diff --git a/test/features/SeqMem.fir b/test/features/SeqMem.fir
index 9690f2d1..354bd8de 100644
--- a/test/features/SeqMem.fir
+++ b/test/features/SeqMem.fir
@@ -4,21 +4,21 @@ circuit Top :
   module Top : 
     input clk : Clock
     wire i : UInt<5>
-    i := UInt(1)
+    i <= UInt(1)
     wire i0 : UInt<5>
     wire j : UInt<128>
 
-    i0 := UInt(10)
+    i0 <= UInt(10)
 
     cmem m-com : UInt<128>[32], clk
     infer accessor r-com = m-com[i]
     infer accessor w-com = m-com[i]
-    j := r-com
-    w-com := j
+    j <= r-com
+    w-com <= j
 
 
     smem m-seq : UInt<128>[32], clk
     infer accessor r-seq = m-seq[i]
     infer accessor w-seq = m-seq[i]
-    j := r-seq
-    w-seq := j
+    j <= r-seq
+    w-seq <= j
diff --git a/test/features/TwoClocks.fir b/test/features/TwoClocks.fir
index 9665c153..f68a2769 100644
--- a/test/features/TwoClocks.fir
+++ b/test/features/TwoClocks.fir
@@ -8,14 +8,14 @@ circuit Top :
     reg src : UInt<10>, clk1, reset1
     reg sink : UInt<10>, clk2, reset2
 
-    onreset src := UInt(0)
-    src := addw(src,UInt(1))
+    onreset src <= UInt(0)
+    src <= addw(src,UInt(1))
 
     reg sync_A : UInt<10>, clk2, reset2
-    sync_A := src
+    sync_A <= src
     reg sync_B : UInt<10>, clk2, reset2
-    sync_B := sync_A
+    sync_B <= sync_A
 
-    sink := sync_B
+    sink <= sync_B
 
 ;CHECK: Done!