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2016-01-28Fixed bug where subaccess indexes were being classified as female,azidar
mucking up the chirrtl->firrtl transform. #56.
2016-01-28Changed rmode to wmodeazidar
2016-01-28Use IsInvalid instead of Poisons in chirrtl -> firrtl transformazidar
2016-01-28Fixed bug where you cannot extract from a single bit wire in verilog. #55.azidar
2016-01-28Fixed bug where needed to cast bit-operation inputs prior to verilog emissionazidar
2016-01-28Added addw to working ir as an optimized verilog emissionazidar
2016-01-28Add map of symbol->symbol for wdefinstanceazidar
2016-01-28Fixed matching on types for and, or, and xorazidar
2016-01-28Fixed bug and updated test for changing mod to remazidar
2016-01-28Changed mod to remazidar
2016-01-28Updated with new primops. Removed addw,subw,quo,rem,bit. Added ↵azidar
head,tail,asClock.
2016-01-28Fixed readwriter syntax, and all printed mstats to use => instead of a colonazidar
2016-01-28Changed register syntax for optional reset and init valuesazidar
2016-01-27Reworked readwriter typesazidar
2016-01-27Fixed additional tests and inferring rdwr ports in chirrtljackkoenig
2016-01-27Merge branch 'scala-new-mem'jackkoenig
2016-01-25Fixed bug where poisons were not being declaredazidar
2016-01-25Added verilog rename passazidar
2016-01-25Added isinvalid and validifazidar
2016-01-25Removed println in expand whenazidar
2016-01-25Fixed width inference bug for muxesazidar
2016-01-25Removed random printlnazidar
2016-01-25Fixed support for muxes and nodes with passive aggregate typesazidar
2016-01-25Changed first generated name to use _0 postfixazidar
2016-01-24Made CInfer robust to high firrtl errorsazidar
2016-01-24Added muxing on passive aggregate typesazidar
2016-01-24Merge branch 'new-mem' of github.com:ucb-bar/firrtl into new-memazidar
2016-01-24Removed hashing as it made refchip slower to compileazidar
2016-01-24Added DefMemory to CInfer Typesazidar
2016-01-23Fix Verilog syntax errors for print/stopAndrew Waterman
2016-01-23Removed buggy optimization of dshr and dshlazidar
2016-01-23Moved inst declarations after other declarationsazidar
2016-01-23Fixed commas for instances in verilogazidar
2016-01-23Added more semicolonsazidar
2016-01-23Added semicolon after assigns in verilogazidar
2016-01-23off by one error when emitting ports in verilogazidar
2016-01-23Fixed combinational read verilog backendazidar
2016-01-23Removed more prints ;)azidar
2016-01-23Removed print statementsazidar
2016-01-23Fixed bug where the write mask wasn't being generated correctlyazidar
2016-01-23Removed debugging printlnsazidar
2016-01-23Added inference to mportsazidar
2016-01-23Added prefix checker, now compliant with firrtl specazidar
2016-01-23Changed chirrtl to not require known mask valuesazidar
2016-01-20WIP, need to update chirrtl with new mask syntaxazidar
2016-01-17Forgot to add the changesazidar
2016-01-17Removed temporary filesazidar
2016-01-17BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed testsazidar
2016-01-16Add warning that -p unusedducky
2016-01-16Clean up old logging remnantsducky
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