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AgeCommit message (Expand)Author
2017-01-20Remove merging of source locators during module deduplicationJack
2017-01-20Add MultiInfo. Speedup Info concatenation. Fixes #391Jack
2017-01-20Merge branch 'master' into scaladocrootJim Lawson
2017-01-19Merge branch 'master' into addmiddlefirrtlcompilerJim Lawson
2017-01-19Verilog rem fix (#404)grebe
2017-01-19Merge branch 'master' into addmiddlefirrtlcompilerJim Lawson
2017-01-05Fix ScalaDoc complaints; add sbt-site, sbt-ghpages boilerplate.Jim Lawson
2016-12-15Delete annotationsTestFile after test (#405)Leonard Truong
2016-12-14Merge branch 'master' into addmiddlefirrtlcompilerJim Lawson
2016-12-14Remove scalpels.Jim Lawson
2016-12-14Add support for top-level use of MiddleFirrtlCompiler.Jim Lawson
2016-12-14Added NoDedup annotation and test (#397)Adam Izraelevitz
2016-12-13Add MaxWidth of 1,000,000 bitsjackkoenig
2016-12-13Move CheckWidths to its own filejackkoenig
2016-12-08Copy (explicitly) test resource to targetdir. (#392)Jim Lawson
2016-12-08Clk2clock - rename the implicit "clk" module input "clock" (#387)Jim Lawson
2016-12-07Bugfix: add Neg to high form check (#384)Adam Izraelevitz
2016-12-06Fixes for Annotation serialized/deserialize (#390)Chick Markley
2016-12-05Add check for muxing between clocks (#360)Jack Koenig
2016-12-05Bugfix: expand whens not voiding memories (#380)Adam Izraelevitz
2016-11-30Bugfix: Dedup aggressively (ignore comments) (#375)Adam Izraelevitz
2016-11-23Stringified annotations (#367)Adam Izraelevitz
2016-11-21Bugfix: exponential runtime of pull muxes (#379)Adam Izraelevitz
2016-11-21Rewrote inline xform to fix quadratic perf. bug (#377)Adam Izraelevitz
2016-11-15Fixed multi wiring (#368)Adam Izraelevitz
2016-11-14Fix wrong omitting same clocked nondirect children (#374)Adam Izraelevitz
2016-11-10Added additional optimizationsazidar
2016-11-09Added optimizations to for better width inferenceazidar
2016-11-09Bugfix: removed recursive removal in infer widthsazidar
2016-11-07Clock List Transform (#365)Adam Izraelevitz
2016-11-07Fix annotations (#366)Adam Izraelevitz
2016-11-07make default dir be current directory (#361)Chick Markley
2016-11-07Added underscore to GEN, now its _GEN (#362)Adam Izraelevitz
2016-11-05Fix CHIRRTL bugs (#355)Donggyu
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
2016-11-04Add a pass to deduplicate modulesazidar
2016-11-04Refactor Compilers and Transformsjackkoenig
2016-11-03Added Legalize to MiddleToLowFirrtlazidar
2016-11-01Fix Match Error in Check Types on Partial Connect (#359)Jack Koenig
2016-11-01fix bug. remove spurious connect that reassigns node (#358)Scott Beamer
2016-10-31Fixed Verilog emission of andr, orr, and xorr (#357)Adam Izraelevitz
2016-10-30Cleanup fixed point tests (#339)Jack Koenig
2016-10-30Keep package name + directory structure consistent (#354)Colin Schmidt
2016-10-27Wiring (#348)Adam Izraelevitz
2016-10-26Improve reference & name resolution in ReplSeqMem (#352)Donggyu
2016-10-26Add RawString ExtModule parameter supportjackkoenig
2016-10-26Add Support for Parameterized ExtModules and Name Overridejackkoenig
2016-10-26Add ExtModule Testsjackkoenig
2016-10-26Improve integration test API and add support for Verilog resourcesjackkoenig
2016-10-25Logger 1 (#338)Chick Markley
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